Design a Fibonacci number generator that accepts as input a number n on the port numberIn and output the nth Fibonacci number on the output port numberOut. The nth Fibonacci number is the sum of the (n1) and (n2) Fibonacci numbers, and the first two numbers in the sequence are 1 and 1. So the Fibonacci sequence is: 1; 1; 2; 3; 5; 8; 13; 21; : : : Your design should accept the input value of n on the port numberIn when a start signal called start is high for one clock cycle. The reset signal is active low and should be asynchronous. The output consists of the nth Fibonacci number on the port numberOut and a done signal of 1 for one clock cycle indicating that the output is valid. The maximum number of n is 24 and hence the 24rd Fibonacci number is 46; 368. The Fibonacci numbers generator algorithm can be described in the following C-code: unsigned int f i b o n a c c i ( int n){ unsigned int pr evi ous = 0 ; unsigned int cur r ent = 1 ; unsigned int tmp ; unsigned int count = 1 ; while ( count < n) { tmp = cur r ent ; cur r ent = cur r ent + pr evi ous ; pr evi ous = tmp ; count = count + 1 ; }r eturn cur r ent ; } Design a digital system that implement the Fibonacci number generator. Divide your design into data path and control unit. Use SM chart to design your control unit. Requirements You should follow all design and implementation steps. Design Step: Start with the top-level block diagram and identify all external (primary) inputs and outputs for the whole design.

Divide your design into two units: Data Path unit and Control Unit. Iden- tify all the external and internal signals between the two units. Show the design of the Data Path Unit: Identify the required blocks and design them. Show all internal signals. Show the design of the Control Unit: Identify the required control and status signals, use SM chart to design the Control Unit, and connect it to the Data Path. Implementation Step: Implement your design of Data Path and Control Unit using Verilog HDL. Write Verilog modules for each design. Then write Verilog module for the whole system. Test and simulate your design. Your simulation/testing should cover all possibilities.