I need help coding in Verilog. I need to make a 4-bit adder with the following information. I am using EDA Playground for the verilog programming.

t module test; SvVenilog Testbench 1I1 This is the library don't touch! ! 2 IIi you have INV, NAND2, AND2, OR2, NOR2, x0R2, XNOR2 3 111/change start here: this is the deisgn part 4 wire ty: //hint: the connctions between nodules, set them 5 reg ta, tb; //hint: variable you set signals, set them reg 3 module INV (f, a) 4 1nput a; 5 output f; 6: assign #0.2 f- 7 endmodule 9 module NAND2 (f, a, b): 10 input a, b; 10 i1/change End here output f 12 initial begin 12 wire ti 13 nand (t,a,b): 14. assign #0.3 f-t; 15 endmodule 13 Sdumpfile("dump. vcd"); Sdumpvars (1); 16 TI//change start here: this the test part 18 tb 1'b0; 20 t_ " 1.bo; 17 module AND2 (f, a, b); 18 input a, b 19 output f 20 wire t 21 and (t,a,b); 22 assign 80.5f t 23 endnodule ta -1'bi; 25 module NOR2 (f, a, b): 26 input a, b; 27 output f 28 wire t; 29 nor (t,a,b): 30 assign #0.3 f-t; 31 endsodule t.b 1'bl; #10 ////change End here Sdumpoff 33 end 33 module OR2 (f, a, b); 34 input a, b; 35 output f 36 wire ti 37 or (t,a,b) 38 assign #0.5 f-t; 39 endsodule 35 endmodule 41 module XOR2 (f, a, b): 42 input a, b; 43 output f; 44 wire ti 45 xor (t,a,b) 46 assign #0.3 f-t; 47 endmodule 49 module XNOR2 (f, a, b); 50 input a, b 51 output f wire t 53 xnor (t,a,b)