) In this exercise, we assume that the following MIPS code isexecuted on a pipelined processor with a 5-stage pipeline, fullforwarding, and a predict-taken branch predictor:

Label: LW R2, 0(R2)

BEQ R2, R7, Label: Taken once, then not taken

OR R4, R2, R3

SW R4, 0(R5)

a. Draw the pipeline execution diagram for this code, assumingthat branches execute in the EX stage.

b. Assume the branch instructions would be “BEZ Rd,Label” or“BNEZ Rd,Label” where it would branch if the register has ordoes not have a zero value, respectively. Change the abovecode to use these branch instructions instead of BEQ.You can assume that register R8 is available for you to useas a temporary register, and that an SEQ Rdest, Rsrc1,Rsrc2 (set if equal) instruction can be used, it sets registerRdest to 1 if register Rsrc1 equals Rsrc2 and to be 0otherwise.

c. The severity of control hazards can be reduced by movingbranch execution into the ID stage. This approach involves adedicated comparator in the ID stage. However, thisapproach requires additional forwarding logic and hazarddetection. Using the branch instruction in the given code asan example, describe the forwarding and hazard detectionlogic needed to support branch execution in the ID stage.Which type of hazard is this new logic supposed to detect?

d. For the given code, what is the speedup achieved by movingbranch execution into the ID stage? Explain your answer. Inyour speedup calculation, assume that the additionalcomparison in the ID stage does not affect clock cycle time.