In this Multisim lab exercise you will design a common-emitter (CE) amplifier for a specific gain, lower 3DB cut-off frequency and DC collector current using only a single power supply (single supply biasing) Question: (A) Design a CE amplifier with an overall gain of -100V/V, and a DC collector current of 2mA. Choose Ce such that the lower 3dB frequency (f) is 300 Hz (use dominant pole approximation wherein CE contributes to 80% off and CB and Cc each contribute to 10% off. Also, use the largest possible values of R1 and R2. You need to make sure that in your design the error in Ic is less than 5%. You are given VBE-0.6v, p-100, VA-ao The figure below the amplifier circuit we will be designing in the lab. VCC (single supply) Hint: Use Gy'= Av = _ gm (Re ll RL) to find Rc and RL (choose Rc = R.). Note that Aya (open circuit voltage gain) will be twice Av (since Rc RL). Also, Ri does not play any role in the DC bias circuit. (B) Suppose you want to increase the lower 3dB frequency is 3 KHz. Find the new values of the 3 capacitances. (C) Suppose you want to decrease the overall gain to -5V/V. Modify the amplifier circuit. What is the new lower 3dB frequency? (D) Compare the lower 3dB frequencies of parts (B) and (C). Any insights/conclusions