LSB 6 bits 110000(0010100110000000000011000) f eFortheALUand thetwo addunits,whataretheir data in ut values? 2points) Add (Branch) ? ALU Add (PC+4) | Input#? Input#2 20 6 1nput#2 20 Input#1 PC input#2 Input# 1 PC+4 d. What are the values of all inputs for the Registers" unit? (2 points) Read Regel | Read Reg#2 | Write Register | Write Data RegWrite Read register 1 00101-5 Read register 2-01100- C 2, (8 points) In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code x r16,12(r6) lw r16,8(r6) bars,r4,Label # Assume rSt-r4 add r5,r1,r4 at rual pipeline stages hve the foilowing latcies EX 150ps MEM 190ps WB 100ps ID IF 200ps/120ps a. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progres, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the 5-stage pipeline that only has one memory? We have seen that data hazards can be eliminated by adding aop s to the code. Can you do the same with this structural hazard? Why? IF ID EX MEM WB SW 116,12(6) w rl6, 8(r6) beq r5, r4, label IF ID EX MEM WB IF ID EX MEM WB