Ouestion t11 [20 Points) Given the following specifications of a processor that impiemens Tomusulo's algorithin with RoB: - One common data bus (CDB) - 16 ROB entris - Each finctional unit has four reservation stations - One un-pipelined floating point divider, with latency cquals to 8 clock cycles - One 6-stage pipelined floating point unit that can perform addition, substation, and maltiplication - One 2-stage pipelined load-store unit. The first atage is for address calculation and takes one elock cycle. The second stage is for memory access, and it takes three clock cycles. - One integer AL.U whose latency is one clock cycle. A xuume you are given the following code fragment. Fill the following table by showing the eloek cycle number at which each pipeline stage is performed for each instruction in the code fragement. fid 54,0 (sto) fadd, d f5,15,f4 mul, f5,f,f0 mu1, d 512,f0,3 fdiv, d 17,51,f4 fsd f7,0($t0) sub,+0,$0,8