Page of? 0 - 200M Q1. Logical effort c. Unit inverter thi SZ=1 Delay dw2um fanout You are tasked with designing the logic path in lig (a). The NOR gates in the second stage are twice as big as the NAND gates in the second stage The inverter in the first stage is 2x the size of the unit invertor show in fig (c) The delay vs fanout plot of the inverter info (c) is shown in lig (b). 01 (10pts) Design for minimal delay given is 1000x57 and Cin is 2x2 Add extra stages as necessary, while preserving polarity of signal that is driving load. Q1b.(5pt) How much delay do you anticipate through the optimally sized path2 Page of? 0 - 200M Q1. Logical effort c. Unit inverter thi SZ=1 Delay dw2um fanout You are tasked with designing the logic path in lig (a). The NOR gates in the second stage are twice as big as the NAND gates in the second stage The inverter in the first stage is 2x the size of the unit invertor show in fig (c) The delay vs fanout plot of the inverter info (c) is shown in lig (b). 01 (10pts) Design for minimal delay given is 1000x57 and Cin is 2x2 Add extra stages as necessary, while preserving polarity of signal that is driving load. Q1b.(5pt) How much delay do you anticipate through the optimally sized path2