Please use VHDL to code the following.

Table 1: Sign-Magnitude and 2's complement representation Value is Value in 2s Input Output sign- magnitude +0 complement +0 0001 0010 0011 0100 0101 0110 0111 1000 0001 0010 0011 0100 0101 0110 0111 1000 +6 +6 -0 -8 Table 1: Sign-Magnitude and 2's complement representation Value is Value in 2s Input Output sign- magnitude +0 complement +0 0001 0010 0011 0100 0101 0110 0111 1000 0001 0010 0011 0100 0101 0110 0111 1000 +6 +6 -0 -8