Q1.7 branch prediction Points Suppose that we have a 7-stage pipelined architecture that resolves branch outcome and target address in the 3rd stage and if branches are always predicted as not-taken. On the architecture, a 3-cycle stall is expected at every branch misprediction. O True O False Q1.8 addressing mode 3 Points The instruction L.D F2, (4096) uses an addressing mode that is not supported by the MIPS64 ISA. True O False Q1.9 Initiation interval 3 Points Initiation interval is the number of cycles that must elapse between fetching two instructions of a given type. O True O False