Recall that with our 5-stage MIPS pipeline, register reads occur in the second half of the clock cycle while register writes occur in the first half of the clock cycle. Consider the following instruction sequence:

xor $2, $0, $3

slt $5, $2, $4

add $11, $5, $11

lw $8, 0x800($2)

sllv $6, $11, $12

sub $2, $6, $8

a) (5) Assume that the pipeline system employs a hazard detection unit but it does not use data forwarding. If the xor instruction is fetched in clock cycle 1, during which clock cycle does the sub $2, $6, $8 instruction complete its write-back stage? The instructions must be executed in the order shown.

b) (5) Assume that the same instruction sequence is executed again, this time with both a data forwarding unit as well as a hazard detection unit, but with no other techniques to handle data hazards. If the xor instruction is fetched in clock cycle 1, during which clock cycle does the sub $2, $6, $8 instruction now complete its write-back stage?