select the options that true

there is more than one true option

QUESTION 11 A user-visible general purpose register may hold what? OA. an instruction for the processor to execute OB. an address to a word in the text segment cc. the binary encoding of an unsigned integer OD. an address offset QUESTION 12 The control/Status register that holds the address of the next instruction to be fetched is the OA. Instruction Register (IR). 08. Program Counter (PC). oc. Program Status Word (PSH). OD. Address Register (AR). QUESTION 13 Which list depicts the 5-stage MIPS instruction execute pipeline? OA. fetch, execute, memory access, write back B. decode, fetch, execute, write back, memory access se. etch, decode, execute, memory access, write back OD. none of the above QUESTION 14 What is true? A. The Instruction Register holds the most recently fetched instruction. OB. A program interrupt is caught by the kernel and handled by the processor QUESTION 15 Before transfering control to the Interrupt handler routine, the processor must save what in order to resume the previous task? CA. the address of the current instruction B. the address of the next instruction c. the current instruction OD. the next instruction QUESTION 16 Assume the CPU, while handling one interrupt, blocks all incoming interrupts. This strategy doesn't allow for A. prioritizing Interrupts. OB. time-critical needs in a real-time system. QUESTION 17 Multiple programs taking turns in execution on a single CPU is called CA. multitasking or multiprogramming. 8. event-driven programming. oc. multithreading at the processor level. OD. pipelining. QUESTION 18 In cache memory systems, temporal locality means that memory accesses close in time will tend to reference memory locations that are close to each other in RAM. Palse True QUESTION 19 In cache memory systems, spacial locality means that data within relatively close storage locations are more likely to be accessed than data that are farther away. CTrue False ht QUESTION 20 Interrupt-driven I/O means that the DA. processor is responsible to transfer data between RAM and an 1/0 module. OB. 1/0 device transfers its own data. Gent