Systems Architecture

It can be helpful to examine in detail how pipelining affects the underlying clock cycle time of the processor. We will assume that the individual stages of the datapath have specific latencies: IF - 250ps ID - 350ps EX - 150ps MEM - 300ps WB - 200ps

Well assume that the instructions executed by the processor are broken down as follows: ALU/logic - 45% Jump/branch - 20% LDUR - 20% STUR - 15%

What is the total latency of an LDUR instruction in a pipelined and non-pipelined processor? If we can split one stage of the pipelined datapath into two new stages, each with half of the latency of the original stage, which stage would you split and why?

What would be the new clock cycle time of the processor?

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