Task

1. Write inv HDL module to describe four inverters connected to 4-bit busses.

2. Sketch a schematic of the circuit.

Source Code

module main;

reg [3:0]a;

wire [3:0]y;

inv i( .a(a), .y(y) );

initial

begin

$dumpfile("dump.vcd");

$dumpvars(1, main);

$display("Time \t a \t y");

$monitor("%3d \t %b \t %b \t ",$time, a,y);

a=1;

//loop over task 4 times

repeat(4)

begin

change_a;

end

end

task change_a;

begin

#5 a=a+1;

end

endtask

endmodule

Results

Figure 1: Display

Figure 2: Waveform

Log Share 2018-02-26 14:02:18 EST] iverilog '-Wall' design.sv testbench.sv&&unbuffer vvp a.out VCD info: dumpfile dump.vcd opened for output. Time 0001 0010 1101 0011 0100 1011 0101 1010 1110 5 1100 15 20 Finding VCD file.. ./dump.vcd (2018-02-26 14:02:19 EST] Opening EPWave Done