The configuration below for the J-K flip-flops is an application of: HIGH HIGH J QA J QB out CLK CLK K K O up-counter (from 00 to 11) O down-counter (from 11 to 00) O frequency multiplier O frequency dividerQUESTION 9 If we have a 32x8 ROM chip, how many address lines would be available in this chip? 32 0 8 0 5 04 QUESTION 10 One of the following is not true: The design in the programmable logic devices can be tested and changed easier than the fixed logic devices The design can be implemented faster on the fixed logic devices than the programmable logic devices and with less cost. O Fixed logic devices usually take larger physical area than the programmable logic devices O Programmable devices use less expensive tools and software than the fixed logic devices.The time t shown in the figure below, regarding a given flip-flop, is usually referred to as: D CLK O set-up time O propagation delay time O hold time O raise timeQUESTION 7 Using the following diagram, what will be the next state if the current state is' Di Q1 D2 Q CLK O "10" O "00" O "01" O "11"QUESTION 7 Using the following diagram, what will be the next state if the current state is "00". D1 Q1 D2 Q CLK O "10' O "00" O "01" O "11"