The VHDL code for two $1-$bit tristate buffers driving a $1-$bit bus is shown.

$1$ IIBRARY IEEE;

$2$ USE ieee.std$\_$logic$\_1164.$all;

ENTITY eece IS

PORT $(x,$ en : IN STD$\_$LOGIC$\_$VECTOR $(1$ DOWNTO $0)$;

Y : OUT STD$\_$LOGIC$)$;

END;

ARCHITECTURE eece$\_$arch OF eece IS

BEGIN

WITH en $(0)$ SELECT

$yx(0)$ WHEN $\text{'}$ O$\text{'},$

$\text{'}Z\text{'}$ WHEN OTHERS;

WITH en$(1)$ SELECT

$yx(1)$ WHEN $\text{'}0\text{'},$

$\text{'}Z\text{'}$ WHEN OTHERS;

$16$ END;

Write the VHDL code that implements $2561-$bit tristate buffers driving a $1-$bit bus. To ensure there is no syntax errors and correct operations, use the Altera tools to simulate your code. Use GENERATE to create a loop.