This is all part of the questions

Consider an architecture that has 8 interrupt priority levels. The interrupt handler for every device enables interrupts before executing the device-specific code. The below diagram shows three devices. Smaller numbers represent a higher priority level. B is electrically closer to the processor than C. The INTA line is chained through the B and C. A schedule of signals is shown below. Each handler takes 1000 cycles. (i) In what order are the three devices acknowledged? Explain your answer. (4 points) (ii) Assuming that these are the only interrupts, in what order do the interrupt handlers complete? Explain your answer. ( 6 points)