This MIPS question! really rush in time now! need answer for this question and please account in detail. Thank you so much!!!!!

Problem: A process has the following features:

Note: no need to consider the instruction cache, only the data cache.

40% of the instructions are for data moving: i.e. lw/sw, etc. L1 data cache hit time is 1ns L1 cache miss rate is 10% A miss from the L1 cache results in an access to the L2 data cache with these two assumptions. 1. A hit in the L2 data cache takes 3.5ns 2. The L2 data cache miss rate is 30%

A miss from the L2 data cache results in a main memeory access with 100ns of additional penalty time.

I. What is the AMAT (Avg. Memory-Access Time) for this processor? Show calculations.

II. Assume that the clock cycle time is equivalent to the L1 data cache hit time. Given a base CPI of 2.0 without any memory stalls, what is the actual CPI considering the delay caused by data memory accesses?