A 16-K NMOS RAM, with the cell design shown in Figure 16.74(b), is to dissipate no more than \(200 \mathrm{~mW}\) in standby when biased at \(V_{D D}=2.5 \mathrm{~V}\). Design the width-to-length ratios of the transistors and the resistance value. Assume \(V_{T N}=0.7 \mathrm{~V}\) and \(k_{n}^{\prime}=35 \mu \mathrm{A} / \mathrm{V}^{2}\).

Figure 16.74(b):-

Transcribed Image Text:

D R MA T X Row select VDD D M M (b) MB T X Row select