Consider the CMOS RAM cell and data lines in Figure 16.76 biased at \(V_{D D}=2.5 \mathrm{~V}\). Assume transistor parameters \(k_{n}^{\prime}=80 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=35 \mu \mathrm{A} / \mathrm{V}^{2}\), \(V_{T N}=0.4 \mathrm{~V}, V_{T P}=-0.4 \mathrm{~V}, W / L=2\left(M_{N 1}\right.\) and \(\left.M_{N 2}\right), W / L=4\left(M_{P 1}\right.\) and \(M_{P 2}\) ), and \(W / L=1\) (all other transistors). If \(Q=0\) and \(\bar{Q}=1\), determine the steady-state values of \(D\) and \(\bar{D}\) after the row has been selected. Neglect the body effect.

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VDD Pull-up transistors Mp3 VDD D VDD Mp4 D Mp2 Mp1 MB Q :CD MA CD MN1 MN2 Word line Figure 16.76 CMOS RAM cell including PMOS pull-up transistors