Consider the CMOS RAM cell and data lines in Figure 16.76 with circuit and transistor parameters described in Problem 16.90. Assume initially that \(Q=0\) and \(\bar{Q}=1\). Assume the row is selected with \(X=2.5 \mathrm{~V}\) and assume the data lines, through a write cycle, are \(\bar{D}=0\) and \(D=2.5 \mathrm{~V}\). Determine the values of \(Q\) and \(\bar{Q}\) just after the row select has been applied.

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VDD Pull-up transistors Mp3 VDD D VDD Mp4 D Mp2 Mp1 MB Q :CD MA CD MN1 MN2 Word line Figure 16.76 CMOS RAM cell including PMOS pull-up transistors