(a) Redesign the resistive load inverter in Figure 16.3 (a) so that the maximum power dissipation is \(0.25 \mathrm{~mW}\) with \(V_{D D}=3.3 \mathrm{~V}\) and \(v_{O}=0.15 \mathrm{~V}\) when the input is a logic 1 .

(b) Using the results of part (a), what is the input voltage range when the transistor is biased in the saturation region?

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iD VDD VDD RD RD = VDS (sat) VGS VTN -Transition point VDD VDS Figure 16.3 (a) NMOS inverter with resistor load and (b) transistor characteristics and load line