A simple output stage for an NMOS op-amp is shown in Figure P13.38. Device \(M_{1}\) operates as a source follower. The bias voltages are \(V^{+}=3 \mathrm{~V}\) and \(V^{-}=-3 \mathrm{~V}\). Transistor parameters are \(k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=\) \(0.4 \mathrm{~V}\), and \(\lambda=0.025 \mathrm{~V}^{-1}\). Assume that transistors \(M_{2}-M_{5}\) are matched.

(a) Determine the width-to-length ratios of transistors \(M_{2}-M_{5}\) such that \(I_{D Q 2}=0.5 \mathrm{~mA}\).

(b) Determine the \(W / L\) ratio of \(M_{1}\) such that the voltage gain is 0.98 .

(c) If the output resistance of source \(v_{I}\) is \(10 \mathrm{k} \Omega\), determine the output resistance of this output stage.

Transcribed Image Text:

V+ M3 Mi M4 M5 M2 V- Figure P13.38