The circuit in Figure P13.39 is another form of an output stage for the CMOS op-amp shown

Question:

The circuit in Figure P13.39 is another form of an output stage for the CMOS op-amp shown in Figure 13.15. Assume the same transistor parameters as given in Example 13.10. The width-to-length values of some transistors are given and the applied gate-to-source voltages of $M_{5}$ and $M_{9}$ are shown.

(a) What is the bias current $I_{Q 2}$ ?

(b) Determine the $W / L$ ratios of $M_{8 P}$ and $M_{8 N}$ such that the quiescent currents in $M_{6}$ and $M_{7}$ are $25 \mu \mathrm{A}$.

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