Consider the NMOS inverter with depletion load in Figure 16.7(a). Let \(V_{D D}=1.8 \mathrm{~V}\), and assume \(V_{T N D}=0.3 \mathrm{~V}\) and \(V_{T N L}=-0.6 \mathrm{~V}\).

(a) Design the circuit such that the power dissipation is \(80 \mu \mathrm{W}\) and the output voltage is \(v_{O}=0.06 \mathrm{~V}\) when \(v_{I}\) is a logic 1 .

(b) Using the results of part (a), determine the transition points for the driver and load transistors.

(c) If \((W / L)_{D}\) found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is \(v_{O}\) when \(v_{I}\) is a logic 1 ?

Figure 16.7(a):-

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VDD + iDL Load: VDSL VTNL, KL VGSD JiDD + VDSD (a) Driver. VIND, KD