(a) Implement the traffic-light controller of Figure 4-14 using a module 13 counter with added logic. The counter should increment every clock, with two exceptions. Use a ROM to generate the outputs.
(b) Write a Verilog description of your answer to (a). 

(c) Write a test bench for part (b) and verify that your controller works correctly. Use concurrent statements to generate test inputs for Sa and Sb.