Draw the circuit represented by the following Verilog process:
always @(clk,clr)
begin
if(clr == 1'b1)
Q <= 1'b0;
else if(clk == 1'b0 && CE == 1'b1)
begin
if(C == 1'b0)
Q <= A & B;
else
Q <= A | B;
end
end
Why is clr on the sensitivity list whereas C is not?