Consider the following Verilog code:
module Q3(A,B,C,F,Clk,E);
input A,B,C,F,Clk;
output reg E;
reg D,G;
initial
begin
E = 1'b0;
D = 1'b0;
G = 1'b0;
end
always @(posedge Clk)
begin
D <= A & B & C;
G <= ~A & ~B;
E <= D | G | F;
end
endmodule
(a) Draw a block diagram for the circuit (no gates and at block level only).
(b) Give the circuit generated by the preceding code (at the gate level).