Draw the hardware obtained if the following code is synthesized: module reg3 (Q1,Q2,Q3,Q4, A,CLK); input A; input
Question:
Draw the hardware obtained if the following code is synthesized:
module reg3 (Q1,Q2,Q3,Q4, A,CLK);
input A;
input CLK;
output Q1,Q2,Q3,Q4;
reg Q1,Q2,Q3,Q4;
always @(posedge CLK)
begin
Q4 = Q3;
Q3 = Q2;
Q2 = Q1;
Q1 = A;
end
endmodule
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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