Write a Verilog module for one flip-flop in a 74HC374 (octal D-type flip-flop with 3-state outputs. Given the D-type flip-flop setup time = 15 ns, hold time = 5 ns, pulse width time = 15 ns). Assume that all logic values are x, 0, 1, or z. Check setup, hold, and pulse-width specs using monitor statements. Unless the output is z, the output should be x if CLK or OC is x, or if an x has been stored in the flip-flop. The timing checks should be done inside: specify …. Endspecify