(5) [22 pts] Consider two processors with different instruction set architecture, P1 and P2. Processor P1 runs on a clock rate of 2.5 GHz and P2 runs on 3.0 GHz. There are four classes of instructions: arith/logic, load, store, and control, whose CPIs and frequencies of each processor are given in the following table. Instruction class Frequency Frequency Execution CPIs of P1 (base CPI with ideal memory) 0.9 1.2 1.5 1.1 Execution CPIs of P2 (base CPI with ideal memory) 1.0 40% 25% arith/logic load store control 1.4 50% 20% 10% 20% 15% 20% 1.8 1.3 Suppose these two CPUs use separate level one (L1) caches for instructions and data (Harvard memory architecture) with different miss rates for instruction and data access: - A cache hit incurs no stall cycles. - Assume a cache miss rate of 0.6% for instruction fetch and a cache data miss rate of 5% in L1 cache. - The second level of cache could be accessed in 6 clock cycles. - Assume a cache miss rate of 4% for instruction fetch and data access in L2 cache. - While a L2 cache miss incurs 200 stall cycles for memory reads and 300 stall cycles for memory writes respectively. (a) [16 pts] For these two processors, find the AMAT and CPI using this cache. Supposed the same number of instructions is executed by these two processors when running a benchmark, which processor is faster? (6) [6 pts] It is about Amdahl's Law. Suppose that we can improve the Arith Logic instructions performance of machine by a factor of 20 (the same Arith Logic instructions run 20 times faster on this new machine) because we use a new implementation of ALU. Calculate the speedup for these two processors respectively