5.11 This exercise examines the effect of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.4. For these exercises, refer to the sequence of word address shown below. 0x03, 0xb4, 0x2b, 0x02, Oxbe, 0x58, 0xbf, 0x0e, Oxlf, 0xb5, 0xbf, 0xba, 0x2e, Oxce 5.11.1 [10] Sketch the organization of a three-way set associative cachoe with two-word blocks and a total size of 48 words. Your sketch should have a style similar to Figure 5.18, but clearly show the width of the tag and data fields. 5.11.2 [10] Trace the behavior of the cache from Exercise 5.11.1. Assume a true LRU replacement policy. For each reference, identify the binary word address, the tag, the index, the offset I whether the reference is a hit or a miss, and after the reference has been handled. 5.11 This exercise examines the effect of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.4. For these exercises, refer to the sequence of word address shown below. 0x03, 0xb4, 0x2b, 0x02, Oxbe, 0x58, 0xbf, 0x0e, Oxlf, 0xb5, 0xbf, 0xba, 0x2e, Oxce 5.11.1 [10] Sketch the organization of a three-way set associative cachoe with two-word blocks and a total size of 48 words. Your sketch should have a style similar to Figure 5.18, but clearly show the width of the tag and data fields. 5.11.2 [10] Trace the behavior of the cache from Exercise 5.11.1. Assume a true LRU replacement policy. For each reference, identify the binary word address, the tag, the index, the offset I whether the reference is a hit or a miss, and after the reference has been handled