ECE 374 Lab: ADD Instruction The VHDL Code For This Lab Implements A MIPs Processor That Can Only Execute "Add" Instructions. Your Goal For This Lab Is To Encode The Following Sequence Of "Add" Instructions And Load The Instruction Memory With These Instructions. 1. ADD R6, RI, RO 2. ADD R6, R6, R2 3. ADD R6, R6, R3 4. ADD R6, R6, R4 5. ADD R6, R6, R5