Question: First write a Verilog module that implements a 2x1 MUX (multiplexer) and a module that implements 4x1 MUX using 2x1 MUX. Add an extra input

First write a Verilog module that implements a 2x1 MUX (multiplexer) and a module that implements 4x1 MUX using 2x1 MUX. Add an extra input port enable to the 4x1 MUX and 2x1 MUX. Then write another module that implements 8x1 MUX using two 4x1 MUX with enable ports and an or gate. Draw a diagram to show how this is done. Also write test bench programs to test all the multiplexer modules.

Please run the code. Thank you so much!

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