Q C.3(a)-(d) from the H&P textbook. We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality, the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns; ID, 1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns. The pipeline register delay is 0.1 ns. A. What is the clock cycle time of the 5-stage pipelined machine? B. If there is a stall every 4 instructions, what is the CPI of the new machine? C. What is the speedup of the pipelined machine over the single-cycle machine? D. If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle machine