register-file regi Sregi rreg2 Sreg2 Memory ALU address data or Instr. wreg wdata Srt data shift- sign- extend Imm left-2 Target 1. shift left-2 The values of control signals needed during the 2nd clock cycle when the sub instruction is being executed. ct one: a. ALUSEIA=0, AluSelB=01, ALUOP=00, TargetWrit= 1 b. ALUSEIA=0, AluSelB=11, ALUOP=00, TargetWrit=1 C ALUSEIA=0, AluSelB=11, ALUOP=00, TargetWrit=0 d. ALUSEIA=0, AluSelB=11. ALUOP=01, TargetWrit=1 ALUResult Instruction Register ALUResult do English (en) ope rogistor-file regi Sregi rreg2 Sreg2 Memory Srt ALU PC address data or Instr. wreg wdata Srt data sign- shift- left-2 Imm extend Target shift left-2 laim Assume that sw $1, 24 ($2) instruction is executed on this datapath. The content of PC when sw is bein executed is (28)10. What will be the contents of target register at the end of 2nd clock cycle? ect one: a. (124)10 b. (130)to c (176)j0 d. (128)10 Next page ip ALUResult Instruction Register ALUResult