You investigate the possible benefits of a way-predicting L1 cache in this problem. Assume that your current data cache is a 64 KB four-way set associative single banked cache. The system clock cycle time is 0.8 ns and the cache is the cycle time limiter. Assume the hit time is 1 cycles, miss penalty is 11 cycles. Miss rate is 0.0033. As an alternative cache organization, you consider a way-predicted cache modeled as a 64 KB direct-mapped cache with 80% prediction accuracy. If the way prediction is correct, the cache returns result in one cycle. A mispredicted way access that hits in the cache takes one more cycle. The cache has cycle time of 0.6 ns, similar to direct mapped cache. The miss penalty is 18 cycles (because the clock is faster). The miss rate is the same as the rate with the 4-way cache (0.0033). a) What is the average memory access time of the two caches? Calculate AMAT of each cache. Note that the way predicted cache has three outcomes: hit with correct way prediction, hit with way misprediction, and miss. b) Because of the way-predicted cache, the cycle time of the system can be reduced. What is the speed up of way-predicted caches over the current 4-way associated cache? Assume 20% of the instructions are memory accesses. The processor has a single issue pipeline, where memory access is planned for one cycle. The CPI without stalls caused by data memory accesses is 1.3.