For each part of this exercise, assume the initial cache and memory state in Figure 4.42. Each part of this exercise specifies a sequence of one or more CPU operations of the form:
P#:

[<-- ]
Where P# designates the CPU (e.g., P0), is the CPU operation (e.g., read or write),

denotes the memory address, and indicates the new word to be assigned on a write operation.
What is the final state (i.e., coherence state, tags, and data) of the caches and memory after the given sequence of CPU operations has completed? Also, what value is returned by each read operation?
a. P0: read 100
b. P0: read 128
c. P0: write 128 <-- 78
d. P0: read 120
e. P0: read 120 P1: read 120
f. P0: read 120 P1: write 120 <-- 80
g. P0: write 120 <-- 80 P1: read 120
h. P0: write 120 <-- 80 P1: write 120 <-- 90