For each part of this exercise, assume the initial cache and memory state in Figure 5.38. Each part of this exercise specifies a sequence of one or more CPU operations of the form:

P#:

[ ]

where P# designates the CPU (e.g., P0,0), is the CPU operation (e.g., read or write),

denotes the memory address, and indicates the new word to be assigned on a write operation. What is the final state (i.e., coherence state, sharers/owners, tags, and data) of the caches and memory after the given sequence of CPU operations has completed? Also, what value is returned by each read operation?

a. P0,0: read 100

b. P0,0: read 128

c. P0,0: write 128

d. P0,0: read 120

e. P0,0: read 120 P1,0: read 120

f. P0,0: read 120 P1,0: write 120

g. P0,0: write 120

h. P0,0: write 120

Chip 1 Chipo MO M1 Figure 5.37 Multichip, multicore multiprocessor with DSM. P3,1 PO,0 P0,1 Coherency Address 100 00 10 120 000 20 130 108 00 08 108 118 18 L2$, 0 L2$ State Adagss Data Address State Adtagss DM P0.1 DS P3.1 100 10 120 20 DS P0.0: E 108 00 08 DS P3.1: E 108 00 08 DM P1.0 130 10 DS P1,0 118 18 00 20 M1 MO Address State Owner/sharers Data Address State Ownersharers Data DM 00 10 C1 00 20 1000 120 CO, C1 000 08 128 28 00 10 DM CO 00 68 110 130 CO 00 18 00 96 18 138