Questions and Answers of Organization Development

Estimate the improvement in performance that can be achieved if the program in Fig- ure 12.19 is used rather than the program in Figure 12.18. Make some appropriate assumptions about the amount of
Modify the program in Figure 12.19 to make it suitable for execution in a four-processor machine.
Modify the program in Figure 12.20 to make it suitable for execution in a four-processor system.
For small vectors, the approach in Figure 12.19 will be worse than if the dot product is computed using a single processor. Estimate the minimum size of the vectors for which this approach leads to
Repeat Problem 12.14 for the approach in Figure 12.20.
Shared-memory multiprocessors and message-passing multicomputers are architec- tures that support simultaneous execution of tasks that interact with each other. Which of these two architectures can
The Ethernet bus LAN protocol is really only suitable when message transmission time is significantly larger than 2t, where r is the end-to-end bus propagation delay. Consider the case in which
A mailbox memory is a RAM memory with the following feature. A full/empty bit, F/E, is associated with each memory word location. The instructionis executed indivisibly as follows. The F/E bit
Implement the COINCIDENCE function in sum-of-products form, where COINCIDENCE = XOR LO1
Prove the following identities by using algebraic manipulation and also by using truth tables.LO1 (a) abc abc + abc + abc + abc = (b) x+wx=x+w (c) x1x2+2x3 + x3x1 = x1x2+x31
Derive minimal sum-of-products forms for the four 3-variable functionsf, f2, f3, and f4 given in Figure PA.1. Is there more than one minimal form for any of these functions? If so, derive all of
Find the simplest sum-of-products form for the function f using the don't-care conditiond, whereLO1 and d f = x1(x2x3 + x2x3 + x2x3x4) + x2x4(x3 + x1) d=x1x2(x3x4+3x4) + 1x3x4
Consider the function(a) Use a Karnaugh map to find a minimum cost sum-of-products (SOP) expression forf. (b) Find a minimum cost SOP expression for F, which is the complement off. Then, complement
Find a minimum cost implementation of the function f(x1, x2, x3, x4), where f = 1 if either one or two of the input variables have the logic value 1. Otherwise, f = 0.LO1
Figure A.6 defines the 4-bit encoding of BCD digits. Design a circuit that has four inputs labeled b3, ..., bo, and an outputf, such that f = 1 if the 4-bit input pattern is a valid BCD digit;
Two 2-bit numbers A = aao and B = bibo are to be compared by a four-variable function f(a, ao,b, bo). The function f is to have the value 1 wheneverwhere v(X) = x1 x21+xo x 2 for any 2-bit number.
Repeat Problem A.8 for the requirement that f = 1 whenever.LO1 subject to the input constraint v(A) > v(B) v(A) + v(B) 4
Prove that the associative rule does not apply to the NAND operator.LO1
Implement the following function with no more than six NAND gates, each having three inputs.LO1 f=x1x2 + x1x2x3+X1x2x3x4 +12x34 Assume that both true and complemented inputs are available.
Show how to implement the following function using six or fewer two-input NAND gates. Complemented input variables are not available.LO1 f(x1+x3)(x2+x4)
Implement the following function as economically as possible using only NAND gates. Assume that complemented input variables are not available.LO1 f = (x1+x3)(x2+x4)
A number code in which consecutive numbers are represented by binary patterns that differ only in one bit position is called a Gray code. A truth table for a 3-bit Gray code to binary code converter
Implement the XOR function using only 4 two-input NAND gates.
Figure A.37 defines a BCD to seven-segment display decoder. Give an implementation for this truth table using AND, OR, and NOT gates. Verify that the same functions are correctly implemented by the
In the logic network shown in Figure PA.3, gate 3 fails and produces the logic value 1 at its output F1 regardless of the inputs. Redraw the network, making simplificationswherever possible, to
Figure A.16 shows the structure of a general CMOS circuit. Derive a CMOS circuit that implements the functionUse as few transistors as possible. (Hint: Consider series/parallel networks of
Draw the waveform for the output Q in the JK circuit of Figure A.31, using the input waveforms shown in Figure PA.4 and assuming that the flip-flop is initially in the O state.LO1 1 Clock 0 1 J 1 K
Derive the truth table for the NAND gate circuit in Figure PA.5. Compare it to the truth table in Figure A.24b and then verify that the circuit in Figure A.26 is equivalent to the circuit in Figure
Compute both the setup time and the hold time in terms of NOR gate delays for the negative edge-triggered D flip-flop shown in Figure A.29.LO1
In the circuit of Figure A.27a, replace all NAND gates with NOR gates. Derive a truth table for the resulting circuit. How does this circuit compare with the circuit in Figure A.27a?LO1
Figure A.33 shows a shift register network that shifts the data to the right one place at a time under the control of a clock signal. Modify this shift register to make it capable of shifting data
A 4-bit shift register that has two control inputs - INITIALIZE and RIGHT/LEFT- is required. When INITIALIZE is set to 1, the binary number 1000 should be loaded into the register independently of
Derive a three-input to eight-output decoder network, with the restriction that the gates to be used cannot have more than two inputs.LO1
Figure A.35 shows a 3-bit up counter. A counter that counts in the opposite direction (that is, 7, 6, ..., 1, 0, 7, ...) is called a down counter. A counter capable of counting in both directions
Figure A.35 shows an asynchronous 3-bit up-counter. Design a 4-bit synchronous up- counter, which counts in the sequence 0, 1, 2, ..., 15, 0.... Use T flip-flops in your circuit. In the synchronous
A switching function to be implemented is described by the expression(a) Show an implementation off in terms of an eight-input multiplexer circuit. (b) Can f be realized with a four-input multiplexer
Repeat Problem A.28 forLO1 f(x1, x2, x3, x4)=x12x3 + x2x3x4 +14
(a) What is the total number of distinct functions, f(x1, x2, x3), of three binary variables? (b) How many of these functions are implementable with one PAL circuit of the type shown in Figure A.43?
Consider the PAL circuit in Figure A.43. Suppose that the circuit is modified by adding a fourth input variable, x4, whose uncomplemented and complemented forms can be connected to all four AND gates
Complete the design of the up/down counter in Figure A.47 by using the state assignment SO=10, $1 = 11, S2 = 01, and S3 = 00. How does this design compare with the one given in Section A.13.1?LO1
Design a 2-bit synchronous counter of the general form shown in Figure A.50 that counts in the sequence ..., 0, 3, 1, 2, 0, ..., using D flip-flops. This circuit has no external inputs, and the
Repeat Problem A.33 for a 3-bit counter that counts in the sequence ..., 0, 1, 2, 3, 4, 5,0,..., taking advantage of the unused count values 6 and 7 as don't-care conditions in designing the
In Section A.13, D flip-flops were used in the design of synchronous sequential circuits. This is the simplest choice in the sense that the logic function values for a D input are directly determined
Repeat Problem A.34 using JK flip-flops instead of D flip-flops. The general procedure for doing this is provided by the answer to Problem A.35.
Repeat Problem A.34 using JK flip-flops instead of D flip-flops. The general procedure for doing this is provided by the answer to Problem A.35.
In the vending machine example used in Section A.13.4 to illustrate the finite state machine model, a single binary output, z, was used to indicate the dispensing of mer- chandise. Change was not
Finite state machines can be used to detect the occurrence of certain subsequences in the sequence of binary inputs applied to the machine. Such machines are called finite state recognizers. Suppose
Repeat Part a only of Problem A.38 for a machine that is to recognize the occurrence of either of the subsequences 011 and 010 in the input sequence, including the cases where overlap occurs. For
Why is the Wait-for-Memory-Function-Completed step needed when reading from or writing to the main memory?LO1
A processor uses a control sequence similar to that in Figure 7.6. Assume that a memory read or write operation takes the same time as one internal processor step and that both the processor and the
Repeat Problem 7.2 for a machine in which the memory access time is equal to twice the processor clock period.LO1
Assume that propagation delays along the bus and through the ALU of Figure 7.1 are 0.3 and 2 ns, respectively. The setup time for the registers is 0.2 ns, and the hold time is 0. What is the minimum
Write the sequence of control steps required for the bus structure in Figure 7.1 for each of the following instructions: (a) Add the (immediate) number NUM to register R1. (b) Add the contents of
The three instructions in Problem 7.5 have many common control steps. However, some of these control steps occur at different counts of the control step counter. Suggest a scheme that exploits these
Consider the Add instruction that has the control sequence given in Figure 7.6. The processor is driven by a continuously running clock, such that each control step is 2 ns in duration. How long will
The addressing modes of a 32-bit, byte-addressable machine include autoincrement and autodecrement. In these modes, the contents of an address register are either incre- mented or decremented by 1,
Show a possible control sequence for implementing the instruction MUL R1, R2 on the processor in Figure 7.1. This instruction multiplies the contents of the registers R1 and R2, and stores the result
Show the control steps for the Branch-on-Negative instruction for a processor that has the structure given in Figure 7.8.LO1
Show the control steps needed to implement the Branch-to-Subroutine instruction of one of the processors described in Chapter 3. Assume that processor has the internal organization of Figure 7.1.LO1
Repeat Problem 7.11 for the processor in Figure 7.8.LO1
Figure 7.3 shows an edge-triggered flip-flop being used for implementing the processor registers. Consider the operation of transferring data from one register to another. Examine the timing of this
The multiplexer and feedback connection in Figure 7.3 eliminate the need for gating the clock input as a means for enabling and disabling register input. Using a timing diagram, explain the problems
Assume that the register file in Figure 7.8 is implemented as a RAM. At any given time, a location in this RAM can be accessed for either a read or a write operation. During the operation R1 [R1] +
The Run signal in Figure 7.11 is set to 0 to prevent the control step counter from being advanced while waiting for a memory read or write operation to be completed. Examine the timing diagram in
The MDR in E control signal is asserted following a clock cycle in which the control signal Read is asserted and is negated when the memory transfer is completed, as shown in Figure 7.5. Design a
Consider a 16-bit, byte-addressable machine that has the organization of Figure 7.1. Bytes at even and odd addresses are transferred on the high- and low-order 8 bits of the memory bus, respectively.
Design an oscillator using an inverter and a delay element. Assuming that the delay element introduces a delay T, what is the frequency of oscillation? Modify the oscillator circuit such that
Some control steps in a processor take longer to complete than others. It is desired to generate a clock signal controlled by a signal called Long/Short such that the duration of a control step is
The output of a shift register is inverted and fed back to its input, to form a counting circuit known as a Johnson counter. (a) What is the count sequence of a 4-bit Johnson counter, starting with
An ALU of a processor uses the shift register shown in Figure P7.1 to perform shift and rotate operations. Inputs to the control logic for this register consist ofAll shift and load operations are
The digital controller in Figure P7.2 has three outputs, X, Y, and Z, and two inputs, A and B. It is externally driven by a clock. The controller is continuously going through the following sequence
Write a microroutine, such as the one shown in Figure 7.21, for the instruction MOV X(Rsrc), Rdst where the source and destination operands are specified in indexed and register ad- dressing modes,
A BGT (Branch if > 0) machine instruction has the expression Z + (NV) = 0 as its branch condition, where Z, N, and V are the zero, negative, and overflow condition flags, respectively. Write a
Write a combined microroutine that can implement the BGT (Branch if > 0), BPL (Branch if Plus), and BR (Branch Unconditionally) instructions. The branch conditions for the BGT and BPL instructions
Figure 7.21 shows an example of a microroutine in which bit-ORing is used to modify microinstruction addresses. Write an equivalent routine, without using bit-ORing, in which conditional branch
Show how the microprogram in Figure 7.20 should be modified to implement the 68000 microprocessor instruction ADD src, Rdst LO1
Explain how the flowchart in Figure 7.20 can be modified to implement the general instruction MOVE src,dst in which both the source and the destination can be in any of the five address modes
Figure P7.3 gives part of the microinstruction sequence corresponding to one of the machine instructions of a microprogrammed computer. Microinstruction B is followedby C, E, F, or I, depending on
It is desired to reduce the number of bits needed to encode the control signals in Figure 7.19. Suggest a new encoding that reduces the number of bits by two. How does the new encoding affect the
Suggest a new encoding for the control signals in Figure 7.19 that reduces the number of bits needed in a microinstruction to 12. Show the effect of the new encoding on the control sequences in
Suggest a format for microinstructions, similar to Figure 7.19, if the processor is orga- nized as shown in Figure 7.8.LO1
What are the relative merits of horizontal and vertical microinstruction formats? Relate your answer to the answers to Problems 7.31 and 7.32.LO1
What are the advantages and disadvantages of hardwired and microprogrammed control?LO1
Consider the following sequence of instructionsIn all instructions, the destination operand is given last. Initially, registers RO and R2 contain 2000 and 50, respectively. These instructions are
Repeat Problem 8.1 for the following program:LO1 Add #20,R0,R1 Mul #3,R2,R3 And #$3A,R1,R4 Add RO,R2,R5
Instruction 12 in Figure 8.6 is delayed because it depends on the results of I. By occupying the Decode stage, instruction I2 blocks I3, which, in turn, blocks I4. Assuming that I3 and 14 do not
The delay bubble in Figure 8.6 arises because instruction I2 is delayed in the Decode stage. As a result, instructions I3 and I are delayed even if they do not depend on either I or 12. Assume that
Figure 8.4 shows an instruction being delayed as a result of a cache miss. Redraw this figure for the hardware organization of Figure 8.10. Assume that the instruction queue can hold up to four
A program loop ends with a conditional branch to the beginning of the loop. How would you implement this loop on a pipelined computer that uses delayed branching with one delay slot? Under what
The branch instruction of the UltraSPARC II processor has an Annul bit. When set by the compiler, the instruction in the delay slot is discarded if the branch is not taken. An alternative choice is
A computer has one delay slot. The instruction in this slot is always executed, but only on a speculative basis. If a branch does not take place, the results of that instruction are discarded.
Rewrite the sort routine shown in Figure 2.34 for the SPARC processor. Recall that the SPARC architecture has one delay slot with an associated Annul bit and uses branch prediction. Attempt to fill
Consider a statement of the formWrite a sequence of assembly language instructions, first using branch instructions only, then using conditional instructions such as those available on the ARM
The feed-forward path in Figure 8.7 (blue lines) allows the content of the RSLT register to be used directly in an ALU operation. The result of that operation is stored back in the RSLT register,
Write the program in Figure 2.37 for a processor in which only load and store in- structions access memory. Identify all dependencies in the program and show how you would optimize it for execution
Assume that 20 percent of the dynamic count of the instructions executed on a computer are branch instructions. Delayed branching is used, with one delay slot. Estimate the gain in performance if the
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots 85 percent of the time and can fill the second slot only 20 percent of the time. What is the
A pipelined processor uses the delayed branch technique. You are asked to recommend one of two possibilities for the design of this processor. In the first possibility, the processor has a 4-stage
Consider a processor that uses the branch prediction mechanism represented in Fig- ure 8.15b. The initial state is either LT or LNT, depending on information provided in the branch instruction.
Assume that the instruction queue in Figure 8.10 can hold up to six instructions. Redraw Figure 8.11 assuming that the queue is full in clock cycle 1 and that the fetch unit can read up to two

Showing 600 - 700 of 1189