Questions and Answers of Organization Development

Using the format for presenting results that is described in Problem 3.53, give a program trace for the byte-sorting program in Figure 3.50b. Show the contents of registers EDI, ECX, and DL, and list
Rewrite the byte-sorting program in Figure 3.50b as a subroutine that sorts a list of 32-bit positive integers. The calling program should pass the list address to the sub- routine. The first 32-bit
Consider the byte-sorting program of Figure 3.50b. During each pass through a sublist, LIST(j) through LIST(0), list entries are swapped whenever LIST(k) > LIST(j). An alternative strategy is to keep
Assume that the list of student test scores shown in Figure 2.14 is stored in the memory as a linked list as shown in Figure 2.36. Write an IA-32 program that accomplishes the same thing as the
The linked-list insertion subroutine in Figure 3.51 does not check if the ID of the new record matches that of a record already in the list. What happens in the execution of the subroutine if this is
The linked-list deletion subroutine in Figure 3.52 assumes that a record with the ID contained in register RIDNUM is in the list. What happens in the execution of the subroutine if there is no record
The input status bit in an interface circuit is cleared as soon as the input data buffer is read. Why is this important?LO1
Write a program that displays the contents of 10 bytes of the main memory in hexadec- imal format on a video display. Use either the assembler instructions of a processor of your choice or
The address bus of a computer has 16 address lines, A15-0. If the address assigned to one device is 7CA416 and the address decoder for that device ignores lines Ag and A9, what are all the addresses
What is the difference between a subroutine and an interrupt-service routine?
The discussion in this chapter assumed that interrupts are not acknowledged until the current machine instruction completes execution. Consider the possibility of suspend- ing operation of the
Three devices, A, B, and C, are connected to the bus of a computer. I/O transfers for all three devices use interrupt control. Interrupt nesting for devices A and B is not allowed, but interrupt
Consider a computer in which several devices are connected to a common interrupt- request line, as in Figure 4.8a. Explain how you would arrange for interrupts from device j to be accepted before the
Consider the daisy chain arrangement in Figure 4.8a. Assume that after a device gen- erates an interrupt request, it turns off that request as soon as it receives the interrupt- acknowledge signal.
Successive data blocks of N bytes each are to be read from a character-oriented input device, and program PROG is to perform some computation on each block of data. Write a control program, CONTROL,
A computer is required to accept characters from 20 video terminals. The main memory area to be used for storing data for each terminal is pointed to by a pointer PNTR, where n = 1 through 20. Input
Consider an I/O device that uses the vectored-interrupt capability of the 68000 processor. (a) Describe the sequence of steps that take place when the processor receives an interrupt request, and
A logic circuit is needed to implement the priority network shown in Figure 4.86. The network handles three interrupt request lines. When a request is received on line INTRI, the network generates an
Interrupts and bus arbitration require means for selecting one of several requests based on their priority. Design a circuit that implements a rotating-priority scheme for four input lines, REQ1
The 68000 processor has a set of three lines called IPL2-0 that are used to signal interrupt requests. The 3-bit binary number on these lines is interpreted by the processor as representing the
(This problem is suitable for use as a laboratory experiment.) Given a video terminal connected to the computer in your laboratory, complete the following two assignments.(a) Write an I/O routine A
(This problem is suitable for use as a laboratory experiment.) In Problem 4.15, when the printing of a sequence is interrupted and later resumed, the sequence continues at the beginning of a new
Consider the breakpoint scheme described in Section 4.2.5. A software-interrupt in- struction replaces a program instruction where the breakpoint is inserted. Before it returns to the original
The software interrupt instruction, SWI, of the ARM can be used by a program to call the operating system to request some service. The service being requested is specified in the low-order 8 bits of
The interrupt-request line, which uses the open-collector scheme, carries a signal that is the logical OR of the requests from all the devices connected to it. In a different application, it is
In some computers, the processor responds only to the leading edge of the interrupt- request signal on one of its interrupt-request lines. What happens if two independent devices are connected to
In the arrangement in Figure 4.20, a device becomes the bus master only when it receives a low-to-high transition on its bus grant input. Assume that device 1 requests the bus and receives a grant.
Assume that in the bus arbitration arrangement in Figure 4.20, the processor keeps asserting BG1 as long as BR is asserted. When device i is requesting the bus, it becomes the bus master only when it
Consider the daisy-chain arrangement shown in Figure P4.1, in which the bus-request signal is fed back directly as the bus grant. Assume that device 3 requests the bus andbegins using it. When device
Shortly after device 3 in Problem 4.23 releases the bus, devices 1 and 5 request the bus simultaneously. Show that they can both receive a bus grant.LO1
Consider the bus arbitration scheme shown in Figure 4.20. Assume that a local signal called BUSREQ in the device interface circuit is equal to 1 whenever the device needs to use the bus. Design the
Consider the arbitration circuit shown in Figure 4.22. Assume that the priority code for a device is stored in a register in the interface circuit. Design a circuit to implement this ar- bitration
How would the timing diagram in Figure 4.26 be affected if the distance between the processor and the I/O device is increased? How can this increased distance be accom- modated in the case of Figure
An industrial plant uses several limit sensors for monitoring temperature, pressure, and other factors. The output of each sensor consists of an ON/OFF switch, and eight such sensors need to be
Design an appropriate interface for connecting a seven-segment display as an output device on a synchronous bus. (See Figure A.37 in Appendix A for a description of a seven-segment display.)LO1
Add an interrupt capability to the interface in Figure 4.29. Show how you can introduce an interrupt enable bit, which can be set or cleared by the processor as bit 6 of the status register of the
The bus of a processor uses the multiple-cycle scheme described in Section 4.5.1. The speed of a memory unit is such that a read operation follows the timing diagram shown in Figure 4.25. Design an
Consider a write operation on a bus that uses the multiple-cycle scheme described in Section 4.5.1. Assume that the processor can send both address and data in the first clock cycle of a bus
Figures 4.24 to 4.26 provide three different approaches to bus design. What happens in each case if the addressed device does not respond due to a malfunction? What problems would this cause and what
In the timing diagram in Figure 4.25, the processor maintains the address on the bus until it receives a response from the device. Is this necessary? What additions are needed on the device side if
Consider a synchronous bus that operates according to the timing diagram in Fig- ure 4.24. The address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus
The time required for a complete bus transfer in the case of Figure 4.26 varies depending on the delays involved. Consider a bus having the same parameters as in Problem 4.35. What is the minimum and
Give a block diagram similar to the one in Figure 5.10 for a 8M 32 memory using 512K x 8 memory chips.LO1
Consider the dynamic memory cell of Figure 5.6. Assume that C = 50 femtofarads (10-15 F) and that leakage current through the transistor is about 9 picoamperes (10-12 A). The voltage across the
In the bottom right corner of Figure 5.8 there are data input and data output registers. Draw a circuit that can implement one bit of each of these registers, and show the required connections to the
Consider a main memory constructed with SDRAM chips that have timing requirements depicted in Figure 5.9, except that the burst length is 8. Assume that 32 bits of data are transferred in parallel.
Criticize the following statement: "Using a faster processor chip results in a correspond- ing increase in performance of a computer even if the main memory speed remains the same."LO1
A program consists of two nested loops - a small inner loop and a much larger outer loop. The general structure of the program is given in Figure P5.1. The decimal memory addresses shown delineate
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four 16-bit words, and each word has an associated 13-bit tag, as shown in Figure P5.2a. When a
Repeat Problem 5.7, assuming only instructions are stored in the cache. Data operands are fetched directly from the main memory and not copied into the cache. Why does this choice lead to faster
A block-set-associative cache consists of a total of 64 blocks divided into 4-block sets. The main memory contains 4096 blocks, each consisting of 128 words. (a) How many bits are there in a main
A computer system has a main memory consisting of 1M 16-bit words. It also has a 4K-word cache organized in the block-set-associative manner, with 4 blocks per set and 64 words per block. (a)
Repeat Problem 5.10, assuming that whenever a block is to be brought from the main memory and the corresponding set in the cache is full, the new block replaces the most recently used block of this
Section 5.5.3 illustrates the effect of different cache-mapping techniques, using the program in Figure 5.19. Suppose that this program is changed so that in the second loop the elements are handled
A byte-addressable computer has a small data cache capable of holding eight 32-bit words. Each cache block consists of one 32-bit word. When a given program is executed, the processor reads data from
Repeat Problem 5.13, assuming that each cache block consists of two 32-bit words. For part (c), use a two-way set-associative cache.LO1
How might the value of k in the interleaved memory system of Figure 5.25b influence block size in the design of a cache memory to be used with the system?LO1
In many computers the cache block size is in the range of 32 to 128 bytes. What would be the main advantages and disadvantages of making the size of cache blocks larger or smaller?LO1
Consider the effectiveness of interleaving with respect to the size of cache blocks. Using calculations similar to those in Section 5.6.2, estimate the performance improvement for block sizes of 16,
Assume a computer has L1 and L2 caches, as discussed in Section 5.6.3. The cache blocks consist of 8 words. Assume that the hit rate is the same for both caches and that it is equal to 0.95 for
Repeat Problem 5.18, assuming that a cache block consists of 4 words. Estimate an appropriate value for C2, assuming that the L2 cache is implemented with SRAM chips.LO1
Consider the following analogy for the concept of caching. A serviceman comes to a house to repair the heating system. He carries a toolbox that contains a number of tools that he has used recently
A 1024 x 1024 array of 32-bit numbers is to be "normalized" as follows. For each column, the largest element is found and all elements of the column are divided by this maximum value. Assume that
Consider a computer system in which the available pages in the physical memory are divided among several application programs. When all the pages allocated to a program are full and a new page is
In a computer with a virtual-memory system, the execution of an instruction may be interrupted by a page fault. What state information has to be saved so that this instruction can be resumed later?
When a program generates a reference to a page that does not reside in the physical main memory, execution of the program is suspended until the requested page is loaded into the main memory. What
A disk unit has 24 recording surfaces. It has a total of 14,000 cylinders. There is an average of 400 sectors per track. Each sector contains 512 bytes of data. (a) What is the maximum number of
The seek time plus rotational delay in accessing a particular data block on a disk is usually much longer than the data flow period for most disk transfers. Consider a long sequence of accesses to
The average seek time and rotational delay in a disk system are 6 ms and 3 ms, re- spectively. The rate of data transfer to or from the disk is 30 Mbytes/sec and all disk accesses are for 8 Kbytes of
Given that magnetic disks are used as the secondary storage for program and data files in a virtual-memory system, which disk parameter(s) should influence the choice of page size?
A tape drive has the following parameters:Estimate the percentage gain in time resulting from the ability to read records in both the forward and backward directions. Assume that records are accessed
Consider the binary numbers in the following addition and subtraction problems to be signed, 6-bit values in the 2's-complement representation. Perform the operations indicated, specify whether or
Signed binary fractions in 2's-complement representation are discussed at the beginning of Section 6.7. (a) Express the decimal values 0.5,-0.123, -0.75, and -0.1 as signed 6-bit fractions. (See
The 1's-complement and 2's-complement binary representation methods are special cases of the (b-1)'s-complement and b's-complement representation techniques in base b number systems. For example,
Represent each of the decimal values 56, -37, 122, and -123 as signed 6-digit numbers in the 3's-complement ternary format, perform addition and subtraction on them in all possible pairwise
A half adder is a combinational logic circuit that has two inputs, x and y, and two outputs, s andc, that are the sum and carry-out, respectively, resulting from the binary addition of x and y. (a)
Write a 68000 or IA-32 program to transform a 16-bit positive binary number into a 5-digit decimal number in which each digit of the number is coded in the binary-coded decimal (BCD) code. These BCD
Assume that four BCD digits, representing a decimal integer in the range 0 to 9999, are packed into the lower half of a 32-bit memory location DECIMAL. Write an ARM, 68000, or IA-32 subroutine to
A modulo 10 adder is needed for adding BCD digits. Modulo 10 addition of two BCD digits, A = A3A2A1A and B = B3B2B Bo, can be achieved as follows: Add A to B (binary addition). Then, if the result is
Show that the logic expression CC-1 is a correct indicator of overflow in the addition of 2's-complement integers, by using an appropriate truth table.LO1
(a) Design a 64-bit adder that uses four of the 16-bit carry-lookahead adders shown in Figure 6.5 along with additional logic to generate C16, C32, C48, and C64, from co and the G and P variables
(a) How many logic gates are needed to build the 4-bit carry-lookahead adder shown in Figure 6.4? (b) Use appropriate parts of the result from Part (a) to calculate how many logic gates are needed to
Show that the worst case delay through an n x n array of the type shown in Figure 6.6b is 6(n-1) 1 gate delays, as claimed in Section 6.3.LO1
Using manual methods, perform the operations Ax B and AB on the 5-bit unsigned numbers A = 10101 and B = 00101.LO1
Show how the multiplication and division operations in Problem 6.13 would be per- formed by the hardware in Figures 6.7a and 6.21, respectively, by constructing charts similar to those in Figures
Write an ARM, 68000, or IA-32 program for the multiplication of two 32-bit unsigned numbers that is patterned after the technique used in Figure 6.7. Assume that the multiplier and multiplicand are
Write an ARM, 68000, or IA-32 program for integer division based on the nonrestoring- division algorithm. Assume that both operands are positive, that is, the leftmost bit is zero for both the
Multiply each of the following pairs of signed 2's-complement numbers using the Booth algorithm. In each case, assume that A is the multiplicand and B is the multiplier.LO1 (a) A 010111 and B =
Repeat Problem 6.17 using bit-pairing of the multipliers.LO1
Indicate generally how to modify the circuit diagram in Figure 6.7a to implement multiplication of signed, 2's-complement, n-bit numbers using the Booth algorithm, by clearly specifying inputs and
If the product of two, n-bit, signed numbers in the 2's-complement representation can be represented in n bits, the manual multiplication algorithm shown in Figure 6.6a can be used directly, treating
An integer arithmetic unit that can perform addition and multiplication of 16-bit un- signed numbers is to be used to multiply two 32-bit unsigned numbers. All operands, intermediate results, and
(a) Calculate the delay, in terms of logic gate delays, for the product bit p7 in each of the arrays in Figure 6.16. Assume that each output from a full adder is available two gate delays after the
Develop the derivation for the formula 1.7log2k - 1.7 for the number of carry-save addition steps needed to reduce k summands to two vectors. (This formula is stated without derivation in Section
(a) How many CSA levels are needed to reduce 16 summands to 2 using a pattern similar to that shown in Figure 6.19? (b) Draw the pattern for reducing 32 summands to 2 to prove that the claim of 8
In Section 6.7, we used the practical-sized 32-bit IEEE standard format for floating- point numbers. Here, we use a shortened format that retains all the pertinent concepts but is manageable for
Consider a 16-bit, floating-point number in a format similar to that discussed in Prob- lem 6.25, with a 6-bit exponent and a 9-bit normalized fractional mantissa. The base of the scale factor is 2
How does the excess-x representation for exponents of the scale factor in the floating- point number representation of Figure 6.24a facilitate the comparison of the relative sizes of two
In Problem 6.25a, conversion of the simple decimal numbers into binary floating-point format is straightforward. However, if the decimal numbers are given in floating-point format, conversion is not
Consider the representation of the decimal number 0.1 as a signed, 8-bit, binary fraction in the representation discussed at the beginning of Section 6.7. If the number does not convert exactly into

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