A clocked T flip-flop has propagation delays from the rising edge of CLK to the changes in Q and Q’ as follows: if Q (or Q’) changes to 1, t_plh = 8 ns, and if Q (or Q’) changes to 0, t_phl = 10 ns. The minimum clock pulse width is t_ck = 15 ns, the setup time for the T input is t_su = 4 ns, and the hold time is t_h = 2 ns. Write a Verilog model for the flip-flop that includes the propagation delay and that reports if any timing specification is violated. Write the model using parameters with default values. The timing checks should be done inside: specify …. Endspecify