(a) For the CMOS inverter in Figure 16.21 in the text, let \(V_{D D}=3.3 \mathrm{~V}\), \(V_{T N}=+0.4 \mathrm{~V}\), and \(V_{T P}=-0.4 \mathrm{~V}\). Assume \((W / L)_{n}=4\) and \((W / L)_{p}=12\). Determine (i) the input switching voltage, (ii) the input voltage when \(v_{O}=3.1 \mathrm{~V}\), and (iii) the input voltage when \(v_{O}=0.2 \mathrm{~V}\).

(b) Repeat part (a) for \((W / L)_{n}=6\) and \((W / L)_{p}=4\).

Transcribed Image Text:

USGP + VDD + iDP VGSN VSDP PMOS: Kp,VTP iDN + NMOS: VDSN KN- VTN Figure 16.21 CMOS inverter