Design the 4-to-1 MUX two ways

1. Write a Verilog module called mux4to1 to implement 4-to-1 multiplexer using functional descriptions and if-else blocks.
2. Write another Verilog module called mux4to1structure to implement the same 4-to-1 multiplexer using structural description and the Verilog build-in logic gates.
3. Design and write a test bench to apply the same inputs to both the mux4to1 and mux4to1structure modules. Name the output of the mux4to1 module f_mux4to1 and the output of mux4to1structure module f_mux4to1structure.
4. Simulate the circuit using ISim and analyze the resulting waveform.
5. Take full screenshots of all Verilog source codes and the resulting simulation waveform to be included in the lab report. Compare the outputs (f_mux4to1 and f_mux4to1structure.) according to all the input combinations and include your analysis in the lab report.