1. Write a Verilog module called myNot to implement the logic NOT gate.
2. Write a test bench to test the myNot module created in step 10. Simulate the circuit using ISim and analyze the resulting waveform.
3. Take full screenshots of the source code of myNot module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.