1. Write a Verilog module called myOr to implement the logic OR gate.
2. Write a test bench to test the myOr module created in step 6. Simulate the circuit using ISim and analyze the resulting waveform.
3. Take full screenshots of the source code of myOr module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Also include your waveform analysis in the lab report.
4. Take full screenshots of the source code of myOr module and the test bench Verilog file to be included in the lab report.