2. [15] This question is regarding the 5-stage MIPS pipeline with data forwarding and hazard detection. [5] Consider the following MIPS code. Mark "X" on instruction(s) for which the ALU uses a forwarded register value, and "S" on instruction(s) for which the pipeline will stall because of data hazard. Assume that all branches are Not-Taken in the execution. a. addi $s1, $s0, -1 slti $to, $sl, 0 bne ?t0, ?zero, exit2 sll $t1, $s1, 2 add $t2, $s2, ?tl lw ?t3, 0 ($t2) lw $t4, 4 (?t2) slt $to, $t4, $t3 beq $to, $zero, exit2