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computer science
systems analysis and design 12th

Questions and Answers of Systems Analysis And Design 12th

Repeat Problem 10.62 for the modified Wilson current mirror in Figure 10.20(b).Data From Problem 10.62:-A Wilson current mirror is shown in Figure 10.20(a). The parameters are: \(V^{+}=5 \mathrm{~V},
Consider the circuit in Figure 10.21 in the text. Assume \(I_{\mathrm{REF}}=50 \mu \mathrm{A}\) and assume transistor parameters of \(V_{T N}=0.8 \mathrm{~V},\left(\frac{1}{2}\right) \mu_{n}
Consider the bias-independent current source in Figure 10.22. Assume transistor parameters of \(V_{T N}=+0.5 \mathrm{~V}, V_{T P}=-0.5 \mathrm{~V},\left(\frac{1}{2}\right) \mu_{n} C_{\mathrm{ox}}=\)
Consider the multitransistor current source in Figure P10.66. The transistor parameters are \(V_{T N}=0.7 \mathrm{~V}, k_{n}^{\prime}=80 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(\lambda=0\). Assume
Consider the circuit shown in Figure P10.67. The transistor parameters are \(V_{T N}=0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(\lambda=0\). Design the \((W / L)\)
The parameters of the transistors in the circuit in Figure P10.68 are \(V_{T N}=0.8 \mathrm{~V}, V_{T P}=-0.8 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=60 \mu
Repeat Problem 10.68 if the bias voltages are changed to \(V^{+}=5 \mathrm{~V}\) and \(V^{-}=-5 \mathrm{~V}\).Data From Problem 10.68:-The parameters of the transistors in the circuit in Figure
Consider the circuit shown in Figure P10.70. The NMOS transistor parameters are \(V_{T N}=0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{n}=0\) and the PMOS transistor
For the circuit shown in Figure P10.70, \(I_{\text {REF }}=100 \mu \mathrm{A}\). The transistor parameters are \(V_{T N}=0.4 \mathrm{~V}, V_{T P}=-0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} /
The parameters of the NMOS transistors in the circuit in Figure P10.72 are \(V_{T N}=0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{n}=0\) and the parameters of the
For the JFET in Figure P10.73, the parameters are: \(I_{D S S}=2 \mathrm{~mA}, V_{P}=\) \(-2 \mathrm{~V}\), and \(\lambda=0.05 \mathrm{~V}^{-1}\). Determine \(I_{O}\) for: (a) \(V_{D}=-5
A JFET circuit is biased with the current source in Figure P10.74. The transistor parameters are: \(I_{D S S}=4 \mathrm{~mA}, V_{P}=-4 \mathrm{~V}\), and \(\lambda=0\). Design the circuit such that
Consider the circuit shown in Figure P10.75. The transistor parameters are \(I_{S 1}=5 \times 10^{-16} \mathrm{~A}, I_{S 2}=10^{-15} \mathrm{~A}, \beta_{1}=180, \beta_{2}=120, V_{A 1}=120
For the circuit shown in Figure P10.76, the transistor parameters are \(V_{T N}=0.5 \mathrm{~V}, V_{T P}=-0.5 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=60 \mu
Consider the simple BJT active load amplifier in Figure 10.29, with transistor parameters: \(I_{S O}=10^{-12} \mathrm{~A}, I_{S 1}=I_{S 2}=5 \times 10^{-13} \mathrm{~A}, V_{A N}=120 \mathrm{~V}\),
The amplifier shown in Figure P10.78 uses a pnp driver and an npn active load circuit. The transistor parameters are: \(I_{S 0}=5 \times 10^{-13} \mathrm{~A}, I_{S 1}=I_{S 2}=\) \(10^{-12}
The bias voltage of the MOSFET amplifier with active load in Figure \(\mathrm{P} 10.79\) is changed to \(V^{+}=3 \mathrm{~V}\). The transistor parameters are \(V_{T N}=\) \(0.5 \mathrm{~V}, V_{T
The simple MOSFET amplifier with active load shown in Figure 10.33 is biased at \(V^{+}=3 \mathrm{~V}\). The reference current is \(I_{\mathrm{REF}}=80 \mu \mathrm{A}\). The transistor parameters are
Consider the circuit shown in Figure 10.37(a). Let \(V^{+}=3 \mathrm{~V}\) and \(R_{1}=\) \(47 \mathrm{k} \Omega\). The transistors \(Q_{1}\) and \(Q_{2}\) are matched with \(V_{E B}(\mathrm{on})=0.6
Again consider the circuit shown in Figure 10.37(a). Let \(V^{+}=5 \mathrm{~V}\) and \(R_{1}=35 \mathrm{k} \Omega\). Let \(V_{E B 1}\) (on) \(=0.6 \mathrm{~V}\). Neglect dc base currents. The
A BJT amplifier with active load is shown in Figure P10.83. The circuit contains emitter resistors \(R_{E}\) and a load resistor \(R_{L}\). (a) Derive the expression for the output resistance looking
In the circuit in Figure P10.84, the active load circuit is replaced by a Wilson current source. Assume that \(\beta=80\) for all transistors, and that \(V_{A N}=120 \mathrm{~V}, V_{A P}=80
For the circuit in Figure 10.40(a), the transistor parameters are \(k_{n}^{\prime}=\) \(80 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=40 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=0.8 \mathrm{~V},
Consider the circuit in Figure 10.40(a). The transistor and circuit parameters are the same as given in Problem 10.85 except for the width-to-length ratios of the transistors. Determine the \(W / L\)
The parameters of the transistors in Figure P10.87 are \(V_{T N}=0.6 \mathrm{~V}\), \(V_{T P}=-0.6 \mathrm{~V}, \quad k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \quad k_{p}^{\prime}=60 \mu
The parameters of the transistors in Figure P10.88 are \(V_{T N}=0.6 \mathrm{~V}\), \(V_{T P}=-0.6 \mathrm{~V}, \quad k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \quad k_{p}^{\prime}=60 \mu
A BJT cascode amplifier with a cascode active load is shown in Figure P10.89. Assume transistor parameters of \(\beta=120\) and \(V_{A}=80 \mathrm{~V}\). The \(V_{B B}\) voltage is such that all
Design a bipolar cascode amplifier with a cascode active load similar to that in Figure P10.89 except the amplifying transistors are to be pnp and the load transistors are to be npn. Bias the circuit
Design a MOSFET cascode amplifier with a cascode active load similar to that shown in Figure P10.88 except that the amplifying transistors are to be PMOS and the load transistors are to be NMOS.
Consider the Widlar current source in Figure 10.9, with parameters given in Example 10.5. Choose appropriate transistor parameters. Connect a \(50 \mathrm{k} \Omega\) resistor between \(V^{+}\)and
Using a computer simulation, verify the results of Example 10.9.Figure 10.17:- Compare the output resistance of the cascode MOSFET current source to that of the two-transistor current source.
Using a computer simulation, verify the results of Example 10.12. In each case, plot \(v_{O}\) versus \(v_{I}\) over the range \(0 \leq v_{I} \leq 1.0 \mathrm{~V}\).Data From Example 10.12:-Figure
Using a computer simulation, verify the results of Problem 10.87.Data From Problem 10.87:-The parameters of the transistors in Figure P10.87 are \(V_{T N}=0.6 \mathrm{~V}\), \(V_{T P}=-0.6
Design a generalized Widlar current source (Figure P10.34) to provide a bias current of \(I_{O}=100 \mu \mathrm{A}\) and an output resistance of \(R_{o}=10 \mathrm{M} \Omega\). The circuit is to be
The current source to be designed has the general configuration shown in Figure 10.17. The bias voltages are \(V^{+}=2.5 \mathrm{~V}\) and \(V^{-}=-2.5 \mathrm{~V}\). The bias current is to be
Design a PMOS version of the current source circuit shown in Figure 10.27. The circuit is to be biased at \(V^{+}=2.5 \mathrm{~V}\) and \(V^{-}=2.5 \mathrm{~V}\). The currents are to be \(I_{O}=0.6
Consider Exercise TYU 10.10. Redesign the circuit such that the small signal voltage gain is \(A_{v}=-120\).Data From Exercise TYU 10.10:-Figure 10.33:- TYU 10.10 Consider the simple MOSFET amplifier
Define differential-mode and common-mode input voltages.
Sketch the dc transfer characteristics of a BJT differential amplifier.
From the dc transfer characteristics, qualitatively define the linear region of operation for a differential amplifier.
What is meant by matched transistors and why are matched transistors important in the design of diff-amps?
Explain how a differential-mode output signal is generated.
Explain how a common-mode output signal is generated.
Define the common-mode rejection ratio, CMRR. What is the ideal value?
What design criteria will yield a large value of CMRR in an emitter-coupled pair?
Sketch the differential-mode and common-mode half-circuit models for an emitter-coupled diff-amp.
Define differential-mode and common-mode input resistances.
Sketch the dc transfer characteristics of a MOSFET differential amplifier.
Sketch and describe the advantages of a MOSFET cascode current source used with a MOSFET differential amplifier.
Sketch a simple MOSFET differential amplifier with an active load.
Explain the advantages of an active load.
Describe the loading effects of connecting a second stage to the output of a BJT diff-amp.
Explain the frequency response of the differential-mode voltage gain.
Sketch a BJT Darlington pair circuit and explain the advantages.
Describe the three stages of a simple BJT operational amplifier.
Discuss the limiting factors for the maximum rated current and maximum rated voltage in a BJT and MOSFET.
Describe the safe operating area for a transistor.
Why is an interdigitated structure typically used in a high-power BJT design?
Discuss the role of thermal resistance between various junctions in a high-power transistor structure.
Define and describe the power derating curve for a transistor.
Define power conversion efficiency for an output stage.
Describe the operation of a class-A output stage.
Describe the operation of an ideal class-B output stage.
Discuss crossover distortion.
What is meant by harmonic distortion?
Describe the operation of a class-AB output stage and why a class-AB output stage is important.
Describe the operation of a transformer-coupled class-A common-emitter amplifier.
Sketch a class-AB complementary BJT push-pull output stage using a \(V_{B E}\) multiplier circuit.
Sketch a class-AB complementary MOSFET push-pull output stage using all MOSFETs.
What are the advantages of a Darlington pair configuration?
Sketch a two-transistor configuration using npn and pnp BJTs that are equivalent to a single pnp BJT.
The maximum current, voltage, and power ratings of a power MOSFET are \(4 \mathrm{~A}, 40 \mathrm{~V}\), and \(30 \mathrm{~W}\), respectively. (a) Sketch and label the safe operating area for this
The common-emitter circuit in Figure P8.2 is biased at \(V_{C C}=24 \mathrm{~V}\). The maximum transistor power is rated at \(P_{Q, \max }=25 \mathrm{~W}\). The other parameters of the transistor are
For the transistor in the common-emitter circuit in Figure P8.2, the parameters are: \(\beta=80, P_{D, \max }=10 \mathrm{~W}, V_{C E(\text { sus) }}=30 \mathrm{~V}\), and \(I_{C, \max }=1.2
Sketch the safe operating region for a MOSFET. Label three arbitrary points on the maximum hyperbola. Assume each of the labeled points is a \(Q\)-point and draw a tangent load line through each
A power MOSFET is connected in a common-source configuration as shown in Figure P8.1. The parameters are: \(I_{D, \max }=4 \mathrm{~A}, V_{D S, \max }=50 \mathrm{~V}\), \(P_{D, \max }=35 \mathrm{~W},
Consider the common-source circuit shown in Figure P8.6. The transistor parameters are \(V_{T N}=4 \mathrm{~V}\) and \(K_{n}=0.2 \mathrm{~A} / \mathrm{V}^{2}\). (a) Design the bias circuit such that
A particular transistor is rated for a maximum power dissipation of \(60 \mathrm{~W}\) if the case temperature is at \(25^{\circ} \mathrm{C}\). Above \(25^{\circ} \mathrm{C}\), the allowed power
A MOSFET has a rated power of \(50 \mathrm{~W}\) and a maximum specified junction temperature of \(150^{\circ} \mathrm{C}\). The ambient is \(T_{\mathrm{amb}}=25^{\circ} \mathrm{C}\). Find the
For a power MOSFET, \(\theta_{\text {dev-case }}=1.5^{\circ} \mathrm{C} / \mathrm{W}, \theta_{\text {snk-amb }}=2.8^{\circ} \mathrm{C} / \mathrm{W}\), and \(\theta_{\text {case
A power BJT must dissipate \(30 \mathrm{~W}\) of power. The maximum allowed junction temperature is \(T_{j, \max }=150^{\circ} \mathrm{C}\), the ambient temperature is \(25^{\circ} \mathrm{C}\), and
The quiescent collector current in a BJT is \(I_{C Q}=3 \mathrm{~A}\). The maximum allowed junction temperature is \(T_{j, \max }=150^{\circ} \mathrm{C}\) and the ambient temperature is
For the class-A amplifier shown in Figure 8.16(a), show that the maximum theoretical conversion efficiency for a symmetrical square-wave input signal is 50 percent.Figure 8.16(a):- Vcc ic RL -O VO o
Consider the emitter-follower amplifier shown in Figure P8.13.(a) Assuming \(\beta \gg 1\), show that the small-signal voltage gain can be written in the form \(A_{v}=\frac{I_{C} R_{L}}{I_{C}
Consider the emitter-follower amplifier shown in Figure P8.13. An average power of \(0.5 \mathrm{~W}\) is to be delivered to a load of \(R_{L}=8 \Omega\). (a) What are the peak values of ac output
Consider the emitter-follower amplifier in Figure P8.13. Since the base-emitter voltage is a function of collector current, the voltage gain changes as the collector current changes. This effect
Consider the class-A emitter-follower circuit shown in Figure P8.16. Assume all transistors are matched with \(V_{B E}(\mathrm{on})=0.7 \mathrm{~V}, V_{C E}(\mathrm{sat})=0.2 \mathrm{~V}\), and
Consider the class-A source-follower circuit shown in Figure P8.17. The transistors are matched with parameters \(V_{T N}=0.5 \mathrm{~V}, K_{n}=12 \mathrm{~mA} / \mathrm{V}^{2}\), and\(\lambda=0\).
A class-A emitter follower biased with a constant current source is shown in Figure P8.16. Assume circuit parameters of \(V^{+}=12 \mathrm{~V}, V^{-}=-12 \mathrm{~V}\), and \(R_{L}=20 \Omega\). The
The circuit parameters for the class-A emitter follower shown in Figure P8.16 are \(V^{+}=24 \mathrm{~V}, V^{-}=-24 \mathrm{~V}\), and \(R_{L}=200 \Omega\). The transistor parameters are \(\beta=50,
Consider the BiCMOS follower circuit shown in Figure P8.20. The BJT transistor parameters are \(V_{B E}(\mathrm{on})=0.7 \mathrm{~V}, V_{C E}(\mathrm{sat})=0.2 \mathrm{~V}, V_{A}=\infty\), and the
For the idealized class-B output stage in Figure 8.18 in the text, show that the maximum theoretical conversion efficiency for a symmetrical squarewave input signal is 100 percent.
Consider an idealized class-B output stage shown in Figure P8.22. (The effective turn-on voltages of devices A and B are zero, and the effective "saturation" voltages of \(v_{A}\) and \(v_{B}\) are
Consider an idealized class-B output stage shown in Figure P8.22. The output stage is to deliver \(50 \mathrm{~W}\) of average power to a \(24 \Omega\) load for a symmetrical input sine wave. Assume
Consider the class-B output stage with complementary MOSFETs shown in Figure P8.24. The transistor parameters are \(V_{T N}=V_{T P}=0\) and \(K_{n}=K_{p}=\) \(0.4 \mathrm{~mA} / \mathrm{V}^{2}\). Let
For the class-B output stage shown in Figure P8.24, the bias voltages are \(V^{+}=12 \mathrm{~V}\) and \(V^{-}=-12 \mathrm{~V}\). The load resistance is \(R_{L}=50 \Omega\), and the transistor
A simplified class-AB output stage with BJTs is shown in Figure 8.24. The circuit parameters are \(V_{C C}=5 \mathrm{~V}\) and \(R_{L}=1 \mathrm{k} \Omega\). For each transistor, \(I_{S}=2 \times
A simplified class-AB output stage with enhancement-mode MOSFETs is shown in Figure 8.26. The circuit parameters are \(V_{D D}=12 \mathrm{~V}\) and \(R_{L}=1 \mathrm{k} \Omega\). The transistor
Consider the class-AB output stage in Figure P8.28. The diodes and transistors are matched, with parameters \(I_{S}=6 \times 10^{-12} \mathrm{~A}\), and \(\beta=40\). (a) Determine \(R_{1}\) such
An enhancement-mode MOSFET class-AB output stage is shown in Figure P8.29. The threshold voltage of each transistor is \(V_{T N}=-V_{T P}=1 \mathrm{~V}\) and the conduction parameters of the output

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