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computer science
systems analysis and design 12th

Questions and Answers of Systems Analysis And Design 12th

Consider the three-terminal voltage regulator in Figure 15.51, with Zener diode voltages of \(V_{Z}=6.3 \mathrm{~V}\). Assume transistor parameters of \(V_{B E}(\mathrm{npn})=\) \(V_{E
The three-terminal voltage regulator in Figure 15.51 has parameters as described in Example 15.16. Assume \(R_{4}=0, V_{A}=50 \mathrm{~V}\) for \(Q_{4}\), and \(r_{z}=15 \Omega\) for \(D_{2}\).
The voltage regulator shown in Figure P15.79 is a variable voltage, 0 to \(5 \mathrm{~A}\) power supply. The transistor parameters are \(\beta=80\) and \(V_{B E}(\mathrm{on})=0.7 \mathrm{~V}\). The
The parameters of the transistor in Figure \(\mathrm{P} 15.80\) are \(\beta=80\) and \(V_{E B}\) (on) \(=0.6 \mathrm{~V}\). The Zener diode is ideal with \(V_{Z}=6.8 \mathrm{~V}\) and the op-amp is
Consider the three-pole high-pass Butterworth active filter described in Exercise TYU 15.1. Using a computer simulation, plot the magnitude of the voltage transfer function versus frequency and
A phase shift oscillator is described in Exercise TYU 15.5. Using a computer simulation, plot the output voltage of the oscillator versus time over several cycles. What is the frequency of
Consider the Schmitt trigger oscillator described in Exercise Ex 15.8. Using a computer simulation, plot the voltage \(v_{X}\) versus time over several cycles. What is the frequency of
A bridge power amplifier is described in Exercise TYU 15.13. Using a computer simulation, plot (a) \(v_{O 1}-v_{O 2}\) versus \(v_{I}\) over the range \(0 \leq v_{I} \leq 4 \mathrm{~V}\) and (b) the
Design a four-pole high-pass Butterworth active filter such that the lowfrequency voltage gain is +20 and the cutoff frequency is \(50 \mathrm{~Hz}\).
Consider the Colpitts oscillator in Figure P15.86. The capacitors \(C_{E}\) and \(C_{B}\) are very large bypass and coupling capacitors. Let \(V_{C C}=5 \mathrm{~V}\). (a) Design the circuit such
Consider the power amplifier in Figure P15.87 with parameters \(V^{+}=15 \mathrm{~V}, V^{-}=-15 \mathrm{~V}\), and \(R_{L}=20 \Omega\). The closed-loop gain must be 10. Design the circuit such that
Consider the simple series-pass regulator circuit in Figure P15.88. Assume an ideal Zener diode with \(V_{Z}=V_{\mathrm{REF}}=4.7 \mathrm{~V}\). Let \(\beta=100\) and \(V_{B E}(\) on \()=0.7
Sketch the quasi-static voltage transfer characteristics of an NMOS inverter with depletion load. What effect does changing the transistor \(W / L\) ratio have on the transfer characteristics?
Sketch an NMOS three-input NOR logic gate. Describe its operation. Discuss the condition under which the maximum logic 0 value is obtained.
Discuss how more sophisticated (compared to the basic NOR and NAND) logic functions can be implemented in a single NMOS logic circuit.
Sketch the quasi-static voltage transfer characteristics of a CMOS inverter. Discuss the various intervals in terms of transistor bias. What is the effect on the transfer curve of changing the
Discuss the parameters that affect the switching power dissipation in a CMOS inverter.
Define the noise margin in a CMOS inverter.
Sketch a CMOS three-input NAND logic gate. Describe its operation. Determine the relative transistor \(W / L\) ratios to obtain equal pull-up and pull-down switching times.
Discuss how more sophisticated (compared to the basic NOR and NAND) logic functions can be implemented in a single CMOS logic circuit.
Discuss the basic principles of a clocked CMOS logic circuit.
Sketch an NMOS transmission gate and describe its operation. What is the maximum output voltage?
Sketch a CMOS transmission gate and describe its operation. Why is the quasistatic output voltage always equal to the quasi-static input voltage?
Discuss what is meant by pass transistor logic.
If an NMOS or CMOS transmission gate is turned off (an open switch), discuss why the output voltage is, in general, not stable.
Sketch an NMOS dynamic shift register and describe its operation.
Sketch a CMOS R-S flip flop and describe its operation. Why must the input condition \(R=S=1\) be avoided?
Describe the basic architecture of a semiconductor random-access memory.
Sketch a CMOS SRAM cell and describe its operation. Discuss any advantages and disadvantages of this design. Describe how the cell is addressed.
Sketch a one-transistor DRAM cell and describe its operation. What makes this circuit dynamic?
Describe a mask-programmed MOSFET ROM memory.
Describe the basic operation of a floating gate MOSFET and how this can be used in an erasable ROM.
Consider the simple MOS op-amp circuit shown in Figure P13.1. The bias current is \(I_{Q}=200 \mu \mathrm{A}\). Transistor parameters are \(k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2},
Consider the simple bipolar op-amp circuit shown in Figure P13.2. The bias current is \(I_{Q}=0.5 \mathrm{~mA}\). Transistor parameters are \(\beta_{n}=180, \beta_{p}=120\), \(V_{B E}\) (on) \(=V_{E
Design the circuit in Figure 13.2 such that the maximum power dissipated in the circuit is \(15 \mathrm{~mW}\) and such that the common-mode input voltage is in the range \(-3 \leq v_{C M} \leq 3
Using the results of Problem 13.3, determine, from a computer simulation, the differential-mode voltage gain of the diff-amp and the voltage gain of the second stage of the op-amp circuit in Figure
Consider the BJT op-amp circuit in Figure P13.5. The transistor parameters are: \(\beta(\mathrm{npn})=120, \beta(\mathrm{pnp})=80, V_{A}=80 \mathrm{~V}\) (all transistors), and baseemitter turn-on
Consider the input stage of the 741 op-amp in Figure 13.4(b).(a) Assume the input voltages are \(V_{1}=0\) and \(V_{2}=+15 \mathrm{~V}\). Consider the B-E voltage of each transistor and determine
For the input stage of the 741 op-amp, assume B-E breakdown voltages of \(5 \mathrm{~V}\) for the npn devices and \(50 \mathrm{~V}\) for the pnp devices. Estimate the differential input voltage at
Consider the bias circuit portion of the 741 op-amp in Figure 13.5. Assume transistor parameters of \(I_{S}=5 \times 10^{-16} \mathrm{~A}\). Neglect base currents.(a) Redesign the circuit such that
Repeat Problem 13.8 for bias voltages of \(\pm 5 \mathrm{~V}\).Data From Problem 13.8:-Consider the bias circuit portion of the 741 op-amp in Figure 13.5. Assume transistor parameters of \(I_{S}=5
Consider the bias circuit shown in Figure P13.10. Let \(V^{+}=3 \mathrm{~V}\), \(V^{-}=-3 \mathrm{~V}, R_{1}=80 \mathrm{k} \Omega\), and \(R_{E}=3.5 \mathrm{k} \Omega\). Assume transistor parameters
The minimum recommended supply voltages for the 741 op-amp are \(V^{+}=5 \mathrm{~V}\) and \(V^{-}=-5 \mathrm{~V}\). Using these lower supply voltages, calculate: \(I_{\mathrm{REF}}, I_{C 10}, I_{C
An expanded circuit diagram of the 741 input stage is shown in Figure 13.6. Assume \(I_{C 10}=50 \mu \mathrm{A}\). If the current gain of the npn transistors is \(\beta_{n}=90\) and the current gain
Consider the 741 op-amp in Figure 13.3, biased with \(V^{+}=15 \mathrm{~V}\) and \(V^{-}=-15 \mathrm{~V}\). Assume that no load is connected at the output, and let the input voltages be zero.
Consider the 741 circuit in Figure 13.3.(a) Determine the maximum range of common-mode input voltage if the bias voltages are \(\pm 15 \mathrm{~V}\).(b) Repeat part (a) if the bias voltages are \(\pm
Consider the output stage of the 741 op-amp shown in Figure 13.8. Assume \(v_{1}=v_{2}=0\) at the input and assume the bias voltages are \(V^{+}=5 \mathrm{~V}\) and \(V^{-}=-5 \mathrm{~V}\). Let
Consider the output stage in Figure P13.16 with parameters \(V^{+}=5 \mathrm{~V}\), \(V^{-}=-5 \mathrm{~V}, R_{L}=10 \mathrm{k} \Omega\), and \(I_{\text {Bias }}=80 \mu \mathrm{A}\). Assume the diode
Figure P13.17 shows a circuit often used to provide the \(V_{B B}\) voltage in the op-amp output stage. Assume \(I_{S}=5 \times 10^{-15} \mathrm{~A}\) for the transistor, \(I_{\text {Bias }}=\) \(120
Assume bias voltages on the 741 op-amp of \(\pm 15 \mathrm{~V}\). (a) Determine the differential-mode voltage gain of the first stage if \(R_{1}=R_{2}=0\). (b) Determine the voltage gain of the
Recalculate the voltage gain of the \(741 \mathrm{op}-\mathrm{amp}\) input stage if \(I_{C 10}=40 \mu \mathrm{A}\).
Assume the 741 op-amp shown in Figure 13.3 is biased at \(\pm 5 \mathrm{~V}\). Using the circuit parameters given in the figure and transistor parameters given in Examples 13.1, calculate the overall
Repeat Problem 13.20 assuming Early voltages of \(100 \mathrm{~V}\).Data From Problem 13.20:-Assume the 741 op-amp shown in Figure 13.3 is biased at \(\pm 5 \mathrm{~V}\). Using the circuit
Consider the output stage of the 741 op-amp shown in Figure 13.8. Assume \(I_{\text {Bias }}=0.18 \mathrm{~mA}\) and assume transistor parameters of \(I_{S}=10^{-14} \mathrm{~A}\) and
The basic bias circuit of the output transistors of the 741 op-amp is shown in Figure P13.23. (a) Sketch the small-signal equivalent circuit. (b) Assuming \(V_{A}=50 \mathrm{~V}\) and using the
Calculate the output resistance of the \(741 \mathrm{op-amp}\) if \(Q_{14}\) is conducting and \(Q_{20}\) is cut off. Assume an output current of \(2 \mathrm{~mA}\).
(a) Determine the differential input resistance of the \(741 \mathrm{op}\)-amp when biased at \(\pm 15 \mathrm{~V}\).(b) Repeat part (a) when the op-amp is biased at \(\pm 5 \mathrm{~V}\).
The frequency response of a particular 741 op-amp shows that the opamp has a phase margin of 70 degrees. If a second single pole exists, in addition to the dominant pole, determine the frequency of
An op-amp that is internally compensated by Miller compensation has a unity-gain bandwidth of \(10 \mathrm{MHz}\) and a low-frequency gain of \(10^{6}\). (a) What is the dominant pole frequency? (b)
A three-stage 741 op-amp has a low-frequency open-loop gain of 200,000 and a dominant pole frequency of \(10 \mathrm{~Hz}\). The second and third poles are at the same frequency. If the phase margin
Consider the simple CMOS op-amp circuit in Figure P13.29 biased with \(I_{Q}=200 \mu \mathrm{A}\). The transistor parameters are \(k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2},
A simple CMOS op-amp circuit is shown in Figure P13.30 with \(I_{Q}=\) \(100 \mu \mathrm{A}\). The transistor parameters are the same as given in Problem 13.29 except for the width-to-length ratios.
Consider the MC14573 op-amp in Figure 13.14. The dc bias currents and small-signal voltage gains were determined in Examples 13.8 and 13.9. Redesign the circuit such that the width-to-length ratio of
Consider the basic diff-amp with active load and current biasing in Figure 13.14. Using the parameters and results of Example 13.8, determine the maximum range of common-mode input voltage under the
The CMOS op-amp in Figure 13.14 is biased at \(V^{+}=5 \mathrm{~V}\) and \(V^{-}=\) \(-5 \mathrm{~V}\). Let \(R_{\mathrm{set}}=50 \mathrm{k} \Omega\). Assume transistor parameters of \(V_{T N}=0.7
For the CMOS op-amp in Figure 13.14, the dc biasing is designed such that \(I_{\text {set }}=I_{Q}=I_{D Q 8}=200 \mu \mathrm{A}\). The transistor parameters are \(V_{T N}=0.5 \mathrm{~V}\), \(V_{T
Consider the MC14573 op-amp in Figure 13.14, with circuit and transistor parameters as given in Examples 13.8 and 13.9. If the compensation capacitor is \(C_{1}=12 \mathrm{pF}\), determine the
The CMOS op-amp in Figure 13.14 has circuit and transistor parameters as given in Problem 13.33. Determine the compensation capacitor required such that the dominant-pole frequency is \(f_{P D}=8
Consider the CMOS op-amp in Figure 13.14, with transistor and circuit parameters as given in Examples 13.8 and 13.9. Determine the output resistance \(R_{o}\) of the open-loop circuit.Data From
A simple output stage for an NMOS op-amp is shown in Figure P13.38. Device \(M_{1}\) operates as a source follower. The bias voltages are \(V^{+}=3 \mathrm{~V}\) and \(V^{-}=-3 \mathrm{~V}\).
The circuit in Figure P13.39 is another form of an output stage for the CMOS op-amp shown in Figure 13.15. Assume the same transistor parameters as given in Example 13.10. The width-to-length values
Consider the three-stage CMOS op-amp in Figure 13.15. Design an allNMOS transistor current source circuit to establish \(I_{Q 1}=150 \mu \mathrm{A}\). The NMOS transistor parameters are
Assume \(I_{\mathrm{REF}}=250 \mu \mathrm{A}\) and \((W / L)_{8}=5\) in the CMOS op-amp shown in Figure 13.15. Determine (a) the quiescent currents in \(M_{6}\) and \(M_{7}\) and (b) the overall
The CMOS folded cascode circuit in Figure 13.17 is biased at \(\pm 5 \mathrm{~V}\) and the reference current is \(I_{\mathrm{REF}}=50 \mu \mathrm{A}\). The transistor parameters are \(V_{T N}=0.5
The CMOS folded cascode amplifier in Figure 13.17 is to be redesigned to provide a differential voltage gain of 10,000 . The biasing is the same as described in Problem 13.42. The transistor
The CMOS folded cascode amplifier of Figure 13.17 is to be designed to provide a differential voltage gain of 25,000 . The maximum power dissipated in the circuit is to be limited to \(3
The bias current in the CMOS current-gain op-amp in Figure 13.18 is \(I_{Q}=120 \mu \mathrm{A}\). The transistor parameters are \(V_{T N}=0.5 \mathrm{~V}, V_{T P}=-0.5 \mathrm{~V}\),
The CMOS current gain op-amp in Figure 13.18 is to be redesigned to provide a differential voltage gain of 400 . The transistor parameters are \(V_{T N}=0.5 \mathrm{~V}, V_{T P}=-0.5 \mathrm{~V},
Redesign the CMOS cascode current mirror in Figure 13.19 to provide a differential voltage gain of 20,000. The bias current and transistor parameters are the same as in Problem 13.46. (a) Design the
A simple BiCMOS amplifier is shown in Figure P13.48. The MOS transistor parameters are \(k_{p}^{\prime}=40 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T P}=-0.4 \mathrm{~V}, \lambda=0\), and \((W /
Consider the simple BiCMOS amplifier shown in Figure P13.49. The bipolar transistor parameters are \(\beta_{n}=\beta_{p}=120, V_{B E}\) (on) \(=V_{E B}(\) on \()=0.7 \mathrm{~V}\), \(V_{A}=\infty\),
A BiCMOS amplifier is shown in Figure P13.50. The transistor parameters \(\operatorname{are} V_{T P}=-0.4 \mathrm{~V}, k_{p}^{\prime}=40 \mu \mathrm{A} / \mathrm{V}^{2}, W / L=40, \lambda=0.035
Design a BiCMOS amplifier that is complementary to the one in Figure P13.50 in that the input devices are NMOS and the load transistors are pnp. Assume transistor parameters of \(V_{T N}=0.4
The reference current in the BiCMOS folded cascode amplifier in Figure 13.20 is \(I_{\mathrm{REF}}=200 \mu \mathrm{A}\) and the circuit bias voltages are \(\pm 10 \mathrm{~V}\). The MOS transistor
The BiCMOS folded cascode amplifier in Figure 13.20 is to be designed to provide a differential voltage gain of 25,000 . The maximum power dissipated in the circuit is to be limited to \(10
If the CA3140 op-amp is biased at \(V^{+}=15 \mathrm{~V}\) and \(V^{-}=-15 \mathrm{~V}\), determine the input common-mode voltage range. Assume B-E voltages of \(0.6 \mathrm{~V}\) for the bipolar
Consider the bias circuit portion of the CA3140 op-amp in Figure 13.22. If \(V_{B E 7}=0.6 \mathrm{~V}\) for \(Q_{7}\) and \(V_{T P}=-1.0 \mathrm{~V}\) for \(M_{8}\), determine the required value of
In the bias portion of the CA1340 op-amp in Figure 13.22, the bipolar transistor parameters are \(V_{B E}(\mathrm{npn})=0.6 \mathrm{~V}\) and \(V_{E B}(\mathrm{pnp})=0.6 \mathrm{~V}\) and the MOSFET
Consider the CA3140 op-amp in Figure 13.21. If the bias currents change such that \(I_{C 5}=I_{C 4}=300 \mu \mathrm{A}\), determine the voltage gains of the input and second stages, and find the
Assume the gain stage of the CA3140 op-amp is modified to include an emitter resistor, as shown in Figure 13.23. Let \(\lambda=0.02 \mathrm{~V}^{-1}\) for \(M_{10}\). If the transistor bias currents
In the LF155 BiFET op-amp in Figure 13.25, the combination of \(Q_{3}, J_{6}\), and \(Q_{4}\) establishes the reference bias current. Assume the power supply voltages are \(V^{+}=10 \mathrm{~V}\) and
Consider the circuit in Figure P13.60. A JFET diff-amp input stage drives a bipolar Darlington second stage. The p-channel differential pair \(J_{1}\) and \(J_{2}\) are connected to the bipolar
Consider the BiFET differential input stage in Figure P13.61, biased with power supply voltages \(V^{+}\)and \(V^{-}\). Let \(V^{+}=-V^{-} \equiv V_{S}\). (a) Design the bias circuit such that
The BiFET diff-amp input stage in Figure P13.61 is biased at \(I_{O 1}=1 \mathrm{~mA}\). The JFET parameters are \(V_{P}=4 \mathrm{~V}, I_{D S S}=1 \mathrm{~mA}\), and \(\lambda=0.02
Consider the input stage and bias circuit of the 741 op-amp in Figure 13.5. Transistor \(Q_{10}\) may be replaced by a constant-current source equal to \(19 \mu \mathrm{A}\). Assume: the npn devices
The output stage of the 741 op-amp is shown in Figure 13.9. Transistor \(Q_{13}\) may be replaced with a constant-current source equal to \(0.18 \mathrm{~mA}\). Use standard transistors. (a) Using a
Consider the BiCMOS input stage of the CA3140 op-amp in Figure 13.21. Transistor \(Q_{5}\) can be replaced with a constant-current source of \(200 \mu \mathrm{A}\). Assume: bipolar transistor
Consider the CMOS op-amp in Figure 13.14. Assume the circuit and transistor parameters are as given in Example 13.8. In addition, let \(\lambda=\) \(0.01 \mathrm{~V}^{-1}\) for all transistors. (a)
Consider the input stage and bias circuit of the 741 op-amp shown in Figure 13.5. Design a complementary circuit such that the input transistors are pnp devices, and the bias currents are \(I_{\text
Redesign the CMOS op-amp in Figure 13.14 to provide a minimum overall voltage gain of at least 50,000 . The bias voltages are \(V^{+}=10 \mathrm{~V}\) and \(V^{-}=-10 \mathrm{~V}\). The threshold

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